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| 型号： | TS-MAC-X2-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 48/66页 |
| 文件大小： | 0K |
| 描述： | SITE LIC ETH MAC 3SPD LATTICEXP2 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACX2UT4 |
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Chapter 5:
Application Support
This chapter provides application support information for the TSMAC IP core.
Test Application Design
The TSMAC IP core evaluation package includes a reference design that can be used to instantiate, simulate, map,
place and route the Lattice TSMAC IP core in an example working design. This reference design provides a loop
back path for packets on the MAC Rx/Tx client interface, through a FIFO and associated logic. Ethernet packets
are sourced to the Rx G/MII and looped back on the MAC Rx/Tx client FIFO interface. Source and destination
addresses in the ethernet frame can be swapped so the looped back packets on the Tx G/MII have the correct
source and destination addresses. This design also provides connections to the other interfaces of the Lattice
TSMAC IP core, including the SMI, Host Bus and Rx/Tx Statistics interfaces. Figure 5-1 shows a block diagram of
the test application design. This loopback design should be able to sustain a 1 Gbps throughput with minimum
sized Ethernet frames.
Figure 5-1. Test Application Design
ts_mac_top.v
sys_clk
TSMAC Support Logic
(buffers, PLLs, dividers, muxes, etc.)
gtx_clk
tx_clk
rx_clk
G/MII
TDI
TMS
Pkt_loop_clksel
rxmac_clk
JTAG
TCK
TDO
txmac_clk
FIFO
cpu_if_gbit_en
reset_n
clk
data_in
ready
Tx Client Intf.
TX G/MII
reset
JTAG/
2048 x 9
Rx Client Intf.
RX G/MII
PAR
Address
Swap
Tri-
Speed
MAC
Core
Host Bus
Orcastra Bus to
MAC Host Bus
and Register
ack
error
retry
data_out
Add_swap
User Slave
NULL
loop_enb
Addres Swap
and Loop Back
Test Logic
Misc. Client signals
Rx/Tx Statistics
hclk
mdc
mdio_en
mdo
mdi
Interface (USI)
User Slave Bus
Orcastra
Bus
SMI
Control
and Status
Register Interface Module
(status/control registers and statistics counters )
hclk
phy_reset_n
IPUG51_03.0, December 2010
48
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J0R-EZ-F2 | CONVERTER MOD DC/DC 7.5V 25W |
| 1487DM3 | WIREWAY 3" NIPPLE 6X6" |
| TS-MAC-SC-UT4 | SITE LICENSE ETH MAC TRI SC/SCM |
| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-XM-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-XM-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-XM-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMBG0505C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|100V V(BO) MAX|DO-215AA |
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