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| 型号： | TS(X)8387VF |
| 厂商： | ATMEL CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封装： | 24 X 24 MM, CERAMIC, QFP-68 |
| 文件页数： | 18/38页 |
| 文件大小： | 617K |
| 代理商： | TS(X)8387VF |
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TS8387
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7. APPLYING THE TS8387
Advanced Application Notes
7.1.
TIMING INFORMATIONS
7.1.1.Timing Values for TS8387F (refer to timing diagram and switching characteristics p8 and p9) :
The min/max timing values are valid over the full temperature range in the following conditions :
Note 1 : Specified Termination Load (Differential output Datas and Data Ready) :
50 ohms resistor in parallel with 1 standard ECLinPS register from Motorola, (e.g : 10E452)
(Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections)
If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corre-
sponding derating value given below.
Note 2 : Output Termination Load derating values for TOD and TDR :
35 ps/pF or 50 ps per additionnal ECLinPS load.
Note 3 :Propagation time delay derating values have also to be applied for TOD and TDR :
6 ps/mm (155 ps/inch) for TSEV8387F Evaluation Board.
Apply proper time delay derating value if a different dielectric layer is used.
7.1.2.Propagation time considerations :
TOD and TDR Timing values are given from Pin to Pin and DO NOT include the additionnal propagation times between
die Pads and input/output termination loads. For the TSEV8387F Evaluation Board, the propagation time delay is 6ps/
mm (155ps/inch) corresponding to 3.4 (@10GHz) dielectric constant of the RO4003 used for the Board.
If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values.
TD does NOT depend on propagation times because it is a differential data.
(TD is the time difference between Data Ready output delay and digital Data output delay)
TD is also the most straightforward data to measure, again because it is differential :
TD can be measured directly onto termination loads, with matched Oscilloscopes probes.
7.1.3.TOD –TDR variation over temperature :
Values for TOD and TDR track each other over temperature ( 1 percent variation for TOD – TDR per 100 degrees Cel-
sius temperature variation ). Therefore TOD – TDR variation over temperature is negligible. Moreover, the internal
(onchip) and package skews between each Data TODs and TDR effect can be considered as negligible.
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and
TDR maximum values. In other terms :
If TOD is at 900 ps, TDR will not be at 1300 ps ( maximum time delay for TDR ).
If TOD is at 1400 ps, TDR will not be at 800 ps ( minimum time delay for TDR ) However, external TOD – TDR values may
be dictated by total digital datas skews between every TODs (each digital data) and TDR :
MCM Board, bonding wires and output lines lengths differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maxi-
mum values for TOD–TDR.
7.1.4.Principle of operation :
Refer to the Specification Timing Diagrams ( Fig.1 p9).
The analog input waveform is sampled and held on the rising edge of the clock input, and the digital data is available
after 2.5 clock periods latency, on the clock falling edge, after a 1000 ps output delay time (TOD). ( To be confirmed at
given temperatures).
The 2.5 period latency is explained by the fact the TS8387 uses both clock edges in its internal timing circuitry, and the
multiple banks of regeneration latches which are used allows for 10 E–18 value for the Bit Error Rate at 500Msps.
TOD is measured from the falling edge zero crossing point of the differential clock input, to the zero crossing point of a
change of the differential data output.
TDR is measured from the rising edge zero crossing point of the differential clock input, to the rising edge zero crossing
point of a change of the DATA READY signal.
High Speed Digital Output Data Storing :
The TS8387 features one single output data port.
The TS8387 data output delay time and Data Ready signal timings have been set up in order to be compatible with fast
ECL data storing registers like for instance the ECLinPS Logic devices from MOTOROLA.
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