参数资料
型号: TS3V555IDT
厂商: STMICROELECTRONICS
元件分类: 模拟波形发生器
英文描述: PULSE; RECTANGULAR, 2 MHz, TIMER, PDSO8
封装: MICRO, PLASTIC, SO-8
文件页数: 8/10页
文件大小: 107K
代理商: TS3V555IDT
TS3V555
7/10
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APPLICATION INFORMATION
MONOSTABLE OPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure 2 the external capac-
itor is initially held discharged by a transistor in-
side the timer.
Figure 2 :
The circuit triggers on a negative-going input sig-
nal when the level reaches 1/3 VCC. Once trig-
gered,the circuit remains in this state until the set
time has elapsed,even if it is triggered again dur-
ing this interval. The duration of the output HIGH
state is given by t = 1.1 R x C.
Notice that since the charge rate and the threshold
level of the comparator are both directly propor-
tional to supply voltage, the timing interval is inde-
pendent of supply. Applying a negative pulse si-
multaneously to the Reset terminal (pin 4) and the
Trigger terminal (pin 2) during the timing cycle dis-
charges the external capacitor and causes the cy-
cle to start over. The timing cycle now starts on the
positive edge of the reset pulse. During the time
the reset pulse is applied, the output is driven to its
LOW state.
When a negative trigger pulse is applied to pin 2,
the flip-flop is set, releasing the short circuit across
the external capacitor and driving the output
HIGH. The voltage across the capacitor increases
exponentially with the time constant
τ = R x C.
When the voltage across the capacitor equals 2/3
VCC, the comparator resets the flip-flop which then
discharges the capacitor rapidly and drives the
output to its LOW state.
Figure 3 shows the actual waveforms generated in
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.
Figure 3 :
VCC
Reset
Trigger
Out
3
2
4
8
7
6
5
1
R
C
Control Voltage
0.01 F
TS3V555
CAPACITOR VOLTAGE = 2.0V/div
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
R = 9.1k , C = 0.01 F , R = 1.0k
L
Do
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se
for
new
design
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