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| 型号： | TS80C51RD2-MCBB |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 41/74页 |
| 文件大小： | 689K |
| 代理商： | TS80C51RD2-MCBB |
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46
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
6.10. Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
6.10.1. Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 24. (SFR0A7h).
Table 23. WDTRST Register
WDTRST Address (0A6h)
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
7
6
5
4
3
2
1
Reset value
X
相关PDF资料 |
PDF描述 |
|---|---|
| TS83C51RB2ZZZ-VCBB | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44 |
| TS80C51RD2-MCLB | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC68 |
| TS83C51RB2ZZZ-LCEB | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| TS87C51RD2-MIMB | 8-BIT, OTPROM, 40 MHz, MICROCONTROLLER, PQFP64 |
| TS87C51RB2-EED | 8-BIT, OTPROM, MICROCONTROLLER, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TS80C51RD2-MCBD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS80C51RD2-MCBR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS80C51RD2-MCE | 功能描述:IC MCU 8BIT 768BYTE 40MHZ 44VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:80C 标准包装:1,500 系列:AVR® ATtiny 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，LIN，SPI，UART/USART，USI 外围设备:欠压检测/复位，POR，PWM，温度传感器，WDT 输入/输出数:16 程序存储器容量:8KB（4K x 16） 程序存储器类型:闪存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 11x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:带卷 (TR) |
| TS80C51RD2-MCEB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS80C51RD2-MCED | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
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