参数资料
型号: TS87C51RD2-MCL
厂商: Atmel
文件页数: 78/84页
文件大小: 0K
描述: IC MCU 8051 OTP 64K 5V 68PLCC
标准包装: 19
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40/20MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 48
程序存储器容量: 64KB(64K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 68-PLCC
包装: 管件
2007-2012 Microchip Technology Inc.
DS70292G-page 81
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.3
System Reset
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 family of devices
have two types of Reset:
Cold Reset
Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in Figure 6-2.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator Mode
Oscillator
Startup Delay
Oscillator Startup
Timer
PLL Lock Time
Total Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD
——
TOSCD
FRCPLL
TOSCD
—TLOCK
TOSCD + TLOCK
XT
TOSCD
TOST
—TOSCD + TOST
HS
TOSCD
TOST
—TOSCD + TOST
EC
——
XTPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
HSPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
ECPLL
TLOCK
SOSC
TOSCD
TOST
—TOSCD + TOST
LPRC
TOSCD
——
TOSCD
Note 1: TOSCD = Oscillator Start-up Delay (1.1
μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4
μs for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
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