参数资料
| 型号： | TS87C51RD2-VIL |
| 厂商： | Atmel |
| 文件页数： | 75/84页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8051 OTP 64K 5V 68PLCC |
| 标准包装： | 19 |
| 系列： | 87C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40/30MHz |
| 连通性： | UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 48 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 68-PLCC |
| 包装： | 管件 |
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2007-2012 Microchip Technology Inc.
DS70292G-page 79
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.2
Reset Control Registers
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1)
R/W-0
U-0
R/W-0
TRAPR
IOPUWR
—
—CM
VREGS
bit 15
bit 8
R/W-0
R/W-1
EXTR
SWR
SWDTEN(2)
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
Unimplemented: Read as ‘0’
bit 9
CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has not occurred
bit 8
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TS87C51RD2-VILB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS87C51RD2-VILD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS87C51RD2-VILR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| TS87C51RD2-VIM | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High Performance 8-bit Microcontroller |
| TS87C51RD2-VIMB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
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