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| 型号： | TSB17BA1 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER |
| 中文描述： | IEEE标准的1394b单端口电缆收发器 |
| 文件页数： | 12/15页 |
| 文件大小： | 218K |
| 代理商： | TSB17BA1 |
SLLS568C JANUARY 2004 REVISED MARCH 2004
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPENDIX A. ERRATA
UTP signal level detection issue
problem description
In some application environments, the TSB17BA1 may respond to input noise that exceeds the internal noise
rejection threshold. Excessive cable length and poor quality components can contribute to the problem. Due
to process variations during manufacture, the sensitivity and threshold levels may vary from device to device.
One or more of the following issues may occur:
1.
Some devices may be sensitive to PCB supply and input signal noise, driving the BETA_OUT pins
continuously. In turn, this may cause the 1394b PHY port connected to the TSB17BA1 to enter a blocked
state, preventing connection when a node is attached to the UTP port.
2.
Some devices may be sensitive to PCB and cable crosstalk from the transmit data path. This crosstalk may
couple into the receive data path during the toning and training process and the 1394b PHY may then
attempt to negotiate with the false crosstalk signal. The 1394b PHY port may enter a blocked state prior
to UTP cable attachment at one or both cable ends.
3.
System or cable noise within the signal bandwidth may translate into a differential signal input to the
TSB17BA1 and falsely generate BETA_OUT signaling. As a result, the 1394b PHY port attached to the
TSB17BA1 may enter a blocked state before connection.
workarounds
The best problem mitigation is to avoid the circumstances that contribute to noise. The phenomenon is highly
dependent on the system and the network environment, so good quality cable, good installation, and good
design practice are critical. Excessively long cable runs must be avoided. Proper connector termination, high
quality components (e.g., low crosstalk transformer), and good PCB layout are important. Please refer to
PCB
Layout Considerations
of this data sheet for more information.
The required workaround is to provide an approximately 51-mV dc offset externally to the UTP input of the
TSB17BA1 device. This may be accomplished by connecting a 1.21-k
, 1% resistor from the UTP5_INN
terminal to signal ground, isolating the transformer from the TSB17BA1 with 0.1-
μ
F capacitors and providing
a 1.3-V common mode voltage. This circuit is shown in Figure 5.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB17BA1PW | 功能描述:1394 接口集成电路 UTP5 Equalizer for 1394b PHYs RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB17BA1PWG4 | 功能描述:1394 接口集成电路 UTP5 Equalizer for 1394b PHYs RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EURO TERMINAL BLOCKS |
| TSB1857CT A3 | 功能描述:两极晶体管 - BJT PNP Transistor Low Vce sat RoHS:否 制造商:STMicroelectronics 配置: 晶体管极性:PNP 集电极—基极电压 VCBO: 集电极—发射极最大电压 VCEO:- 40 V 发射极 - 基极电压 VEBO:- 6 V 集电极—射极饱和电压: 最大直流电集电极电流: 增益带宽产品fT: 直流集电极/Base Gain hfe Min:100 A 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PowerFLAT 2 x 2 |
| TSB19 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EURO TERMINAL BLOCKS |
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