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参数资料
| 型号： | TSL1301 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 3/8页 |
| 文件大小： | 131K |
| 代理商： | TSL1301 |
TSL1301
102
× 1 LINEAR SENSOR ARRAY
WITH HOLD
SOES031A – NOVEMBER 1996 – REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings
Supply voltage, VDD
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input current range, II
– 20 mA to 20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–25
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
Supply voltage, VDD
4.5
5
5.5
V
Input voltage, VI
0
VDD
V
High-level input voltage, VIH
VDD × 0.7
VDD
V
Low-level input voltage, VIL
0
VDD × 0.3
V
Wavelength of light source,
λ
400
700
nm
Clock frequency, fclock
5
2000
kHz
Sensor integration time, tint
0.0515
5
100
ms
Setup time, serial input, tsu(SI)
20
ns
Hold time, serial input, th(SI) (see Note 1)
0
ns
Operating free-air temperature, TA
0
70
°C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
18 Clock Cycles
102 Clock Cycles
CLK
SI
AO
Internal
Reset
Integration
Hi-Z
Not Integrating
Integrating
Figure 1. Timing Waveforms
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