TSS461C
34
Rev. D (22 Feb 01)
M_L [4:0] = 0x00
Linked channel
M_L [4:0] = 0x01
Frame with no DATA field (*)
M_L [4:0] = 0x02
Frame with 1 DATA byte
- - - - - - -
- - - - - - - - - - - - - - - - - - - - - -
M_L [4:0] = 0x1D
Frame with 28 DATA bytes
M_L [4:0] = 0x1E
Frame with 29 DATA bytes
M_L [4:0] = 0x1F
Frame with 30 DATA bytes
(*)
Different of a reply request frame with no in-frame reply (deffered reply)..
CHER:
Channel error status and abort command
As status, this bit is set by the TSS461C when error occurs in
transmission or on a received frame. The user must reset it.
To abort the transmission defined in the channel, this bit can bit set to
1 by the user (see section 13. and 13.3.)
CHTx:
Channel transmitted and transmit enable command
CHRx:
Channel received and receive enable command
The two low order bits of this register contains the message status.
Together with the RNW and RTR bits of the command register
(base_address + 0x01), they define the message type of this channel (see
section 11.). As a general rule (see section 13.3.), the status bits are
only set by the TSS461C, so the user must reset them to perform a
reception (CHRx). The received and
without errors
transmission (CHTx) or/and a
transmitted bits are only set if the corresponding frame is
or if the retry count has been exceeded.
9.3.4. Identifier Mask Registers:
The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison
between the identifier received and the identifier specified.
7
6
5
4
3
2
1
0
ID_M 3
ID_M 2
ID_M 1
ID_M 0
0
0
0
0
7
6
5
4
3
2
1
0
ID_M 11
ID_M 10
ID_M 9
ID_M 8
ID_M 7
ID_M 6
ID_M 5
ID_M 4
Read / Write registers.
ID_M [11:0]:
Identifier Mask
A value of 1 indicates comparison enabled.
A value of 0 indicates comparison disabled.