参数资料
型号: TSS461E
厂商: Atmel Corp.
英文描述: VAN Data Link Controller
中文描述: 凡数据链路控制器
文件页数: 27/57页
文件大小: 817K
代理商: TSS461E
27
TSS461E
4194B–AUTO–12/04
Ma, Mb: Operating mode
command bits
Table 7.
Diagnosis System Command Bits
ETIP: Enable Transmission In
Progress
One: Enable TIP generation
Zero: Disable TIP generation.
The Transmission In Progress (TIP) tells the diagnostic system to enable
transmission diagnosis.
ESDC: Enable System
Diagnosis Clock
One: Enable SDC divider.
Zero: Disable SDC divider.
-The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous
diagnosis.
Command Register (0x03)
Write only register.
Reserved: Bit 1, 2 these bit cannot be set by the user; a zero must always be written
to these bit.
If the circuit is operating at low bit rates there might be a considerable delay
between the writing of this register and the performing of the actual command (worst
case 6 timeslots). The user must verify, by reading the Line Status Register (0x04)
that the commands have been performed.
GRES: General Reset
The Reset circuit command bit performs, if set, exactly as if the external reset pin was
asserted. This command bit has its own auto-reset circuitry.
One: Reset active
Zero: Reset inactive
SLEEP: Sleep Command
If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit
sleep mode, all non-user registers are setup to minimize power consumption and the
oscillator is stopped. To exit from this mode, the user must set either the idle or activate
commands.
is
in
One: Sleep active
Zero: Sleep inactive
Ma
Mb
0
0
Forces the Communication on RxD0 (differential)
0
1
Forces the Communication on RxD2 (DATA)
1
0
Forces the Communication on RxD1 (DATA)
1
1
Automatic selection
7
6
5
4
3
2
1
0
GRES
SLEEP
IDLE
ACTI
REAR
0
0
MSDC
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