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参数资料
| 型号： | TSX88915TMW100 |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| 封装： | CERAMIC, LCC-28 |
| 文件页数： | 5/20页 |
| 文件大小： | 168K |
| 代理商： | TSX88915TMW100 |
TS88915T
13/20
7. Calculation of Total Output-to-Output skew between multiple parts (Part-to-Part Skew)
By combining the tPD specification and the information in Note 5, the worst case Output-to-Output skew between multiple
TS88915’s connected in parallel can be calculated. This calculation assumes that all parts have a common SYNC input
clock with equal delay that input signal to each part. This skew value is valid at the TS88915 output pins only (equally
loaded), it does not include PCB trace delays due to varying loads.
With a 1 M
W resistor tied to analog VCC as shown in Note 4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and –0.5ns. To calculate the skew of any given output between two or more
parts, the absolute value of the distribution of that output given in Table 4 must be subtracted and added to the lower and
upper tPD spec limits respectively. For output Q2, [276–(–44)] = 320ps is the absolute value of the distribution. Therefore
[–1.05 – 0.32] = –1.37ns is the lower tPD limit, and [–0.5 + 0.32] = –0.18ns is the upper limit. Therefore the worst case skew of
output Q2 between any number of part is [(–1.37)–(–0.18)] = 1.19ns. Q2 has the worst case skew distribution of any output,
so 1.2ns is the absolute worst case Output-to-Output skew between multiple parts.
8. Note 4 explains that the tPD specification was measured and is guaranteed for the configuration of the Q/2 output connected
to the FEEDBACK pin and the SYNC input running at 10MHz. The fixed offset (tPD) as described above has some
dependence on the input frequency and what frequency the VCO is running. The graphs of Figure 6 demonstrate this
dependence.
The data presented in Figure 6 is from devices representing process extremes, and the measurements were also taken at
the voltage extremes (VCC = 5.25V and 4.75V). Therefore the data in Figure 6 is a realistic representation of the variation of
tPD.
tPD versus Frequency for Q/2 output fed back,
including process and voltage variation @ 25
°C
(with 1M
W resistor tied to analog VCC)
tPD versus Frequency for Q4 output fed back,
including process and voltage variation @ 25
°C
(with 1M
W resistor tied to analog VCC)
tPD versus Frequency for Q4 output fed back,
including process and voltage variation @ 25
°C
(with 1M
W resistor tied to analog GND)
tPD versus Frequency for Q/2 output fed back,
including process and voltage variation @ 25
°C
(with 1M
W resistor tied to analog GND)
tPD
SYNC to
FEEDBACK
(ns)
–1.50
–1.25
–1.00
–0.75
–0.50
2.5
5.0
7.5
10.0
12.5
15.0
17.5
SYNC INPUT FREQUENCY (MHz)
2.5
5.0 7.5
10 12.5 15 17.5
SYNC INPUT FREQUENCY (MHz)
–1.50
–1.00
–0.50
–2.00
20 22.5 25 27.5
tPD
SYNC to
FEEDBACK
(ns)
2.5
5.0
7.5
10.0
12.5
15.0
17.5
SYNC INPUT FREQUENCY (MHz)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
SYNC INPUT FREQUENCY (MHz)
Figure 7 :
9. The Lock indicator pin (LOCK) will reliably indicate a phase–locked condition at SYNC input frequencies down to 10MHz. At
frequencies below 10MHz, the frequency of correction pulses going into the phase detector from the SYNC and
FEEDBACK pins may not be sufficient to allow the lock indicator circuitry to accurately predict a phase–locked condition.
The TS88915T is guaranteed to provide stable phase–locked operation down to the appropriate minimum input frequency
given in Table 3, even though the LOCK pin may be low at frequencies below 10MHz.
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