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| 型号： | TUA6041-2 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 调谐器 |
| 英文描述： | 3-BAND, VIDEO TUNER, QCC48 |
| 封装： | VQFN-48 |
| 文件页数： | 17/66页 |
| 文件大小： | 926K |
| 代理商： | TUA6041-2 |
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Data Sheet
24
Revision 3.1, 2006-12-19
TUA 6041-2
LIGHTNING
Functional Description
In I
2C-bus mode four different chip addresses can be set by appropriate DC levels at pin
CAS (Chip Address Select), while in 3-Wire mode the chip is addressed by a low active
enable signal at pin EN.
The content of the bus telegram (serial data format) is controlled by software
programming and assigned to the registers of the functional units according to the
several sub addresses. The most significant bit (MSB) of the data protocol is shifted in
first.
The clock is generated by the processor (input pin SCL/Clock), while pin SDA/Data
functions as an input or an output (open drain, external pull-up resistor) depending on
the direction of the data (write or read mode). Both inputs have schmitt-trigger circuits
with hysteresis and furthermore a low-pass characteristic, which suppress a certain
noise level on the bus lines and enhance so the noise immunity of the combi-bus.
A detailed description of the chip address organization in I
2C-mode as well as the used
sub addresses of the data registers is given in chapter 5.2 "Bus Interface" on page 42
- and the programmable I
2C/3-Wire bus data format is shown in chapter 5.3 "Bus Data
3.4.6
DC/DC clock output
To drive a bipolar NPN switching transistor of an external DC/DC converter directly, a
programmable DC/DC clock generator is integrated. The clock frequency and the duty
cycle of the DC/DC clock generator can be set over the I
2C/3-Wire bus as shown in
3.4.7
DAC
Three DACs for digital alignment with a control range up to 5 volt can be programmed in
256 steps as shown in Table 19 "Subaddress 05H, DACs" on Page 56. This voltage
is required for a automatic alignment of the tuner prestage filters as illustrated in
3.4.8
Power-on Reset, Stand-by Condition
While applying the supply voltage, integrated power-on reset circuits ensure a defined
state after initial power-up. The required programming data will be set to default values.
When V
CC fall below approximately 1.2 V (typ.) the power-on resets go active and tie all
write data registers to their power-on defaults (= power-down reset). While power-on
reset is active no programming is possible.
The power-on flags (POFx) are set at power-on and when V
VCCx falls below appr. 1.2 V
(typ.). They will be reset at the end of a READ operation of the status register.
By programmable stand-by control bits it’s possible to reduce the current consumption
of the IC up to 99%. In the full stand-by mode only bus interface is staying active and the
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