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参数资料
| 型号： | TURBO-DECO-E2-U3 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | IP CORE TURBO DECODER EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TURBODECOE2U3 |
Lattice Semiconductor
Turbo Decoder User’s Guide
CCSDS
For CCSDS decoder type, in the case that an external memory is selected; the following additional pins are
required. It is assumed that data and parity are stored in different memory buffers. Non-interleaved and interleaved
parity are stored in different buffers.
Table 5. Additional I/Os Due to External Memory for CCSDS
Port Name
g1_par2_odd1
g2_par2_odd1
g1_par3_odd1
g2_par3_odd1
g1_par3_even1
g2_par3_even1
wren_par3_buf1
wren_par4_buf1
wren_par5_buf1
I/O Type
Input
Input
Input
Input
Input
Input
Output
Output
Output
Width
3-6
3-6
3-6
3-6
3-6
3-6
1
1
1
Signal Description
Parity 3 (systematic) data port 1
Parity 3 (systematic) data port 2
Parity 4 (systematic) data port 1
Parity 4 (systematic) data port 2
Parity 5 (interleaved) data port 1
Parity 5 (interleaved) data port 2
Write enable for parity 3 (systematic)
Write enable for parity 4 (systematic)
Write enable for parity 5 (interleaved)
In the case where double buffer is selected along with the external memory the I/O pins in Table 6 will also be
added to the core for exchanging data with the second buffer in the case of CCSDS.
Table 6. Additional I/Os Due to Double Buffering for CCSDS
Port Name
g1_par2_odd2
g2_par2_odd2
g1_par3_odd2
g2_par3_odd2
g1_par3_even2
g2_par3_even2
wren_par3_buf2
wren_par4_buf2
wren_par5_buf2
I/O Type
Input
Input
Input
Input
Input
Input
Output
Output
Output
Width
3-6
3-6
3-6
3-6
3-6
3-6
1
1
1
Signal Description
Parity 3 (systematic) data port 1
Parity 3 (systematic) data port 2
Parity 4 (systematic) data port 1
Parity 4 (systematic) data port 2
Parity 5 (interleaved) data port 1
Parity 5 (interleaved) data port 2
Write enable for parity 3 (systematic)
Write enable for parity 4 (systematic)
Write enable for parity 5 (interleaved)
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