参数资料
型号: TURBO-DECO-O4-N1
厂商: Lattice Semiconductor Corporation
文件页数: 8/22页
文件大小: 0K
描述: IP CORE TURBO DECODER ORCA 4
标准包装: 1
系列: *
其它名称: TURBODECOO4N1
Lattice Semiconductor
Turbo Decoder User’s Guide
Figure 7. Output Handshake with rfno Signal Going Low
Note: Signals are transferred on the rising edge. N is the block size.
When the decoder is processing data it will lower rfi if it cannot receive another data block. This occurs in two dif-
ferent scenarios. If only a single buffer has been chosen then the decoder will de-assert the rfi signal as soon as
an input data block is read in completely. In case of double buffer memory the decoder will lower rfi when it has
two blocks in memory and one of them is still being processed. Once the decoder completes processing the block,
it will assert both rfo and rfi . As shown in Figure 8, the average processing delay for the Turbo Decoder in the
case of 3GPP is 2.13xBxI, where B is the block size and I is the number of iterations.
Figure 8. Decoder State During Data Processing
Note: Signals are transferred on the rising edge.
8
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