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参数资料
| 型号： | TURBO-DECO-PM-U3 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IP CORE TURBO DECODER ECP2M |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TURBODECOPMU3 |
Lattice Semiconductor
Turbo Decoder User’s Guide
3GPP2
For the 3GPP2 decoder type, in the case that an external memory is selected; the following additional pins are
required. It is assumed that data and parity are stored in different memory buffers. Non-interleaved and interleaved
parity are stored in different buffers.
Table 7. Additional I/Os Due to External Memory for 3GPP2
Port Name
g1_par2_odd1
g2_par2_odd1
g1_par2_even1
g2_par2_even1
wren_par3_buf1
wren_par4_buf1
I/O Type
Input
Input
Input
Input
Output
Output
Width
3-6
3-6
3-6
3-6
1
1
Signal Description
Parity 3 (systematic) data port 1
Parity 3 (systematic) data port 2
Parity 4 (interleaved) data port 1
Parity 4 (interleaved) data port 2
Write enable for parity 3 (systematic)
Write enable for parity 4 (interleaved)
In the case where a double buffer is selected along with the external memory, the I/O pins in Table 8 will also be
added to the core for exchanging data with the second buffer in the case of 3GPP2.
Table 8. Additional I/Os Due to Double Buffering for 3GPP2
Port Name
g1_par2_odd2
g2_par2_odd2
g1_par2_even2
g2_par2_even2
wren_par3_buf2
wren_par4_buf2
I/O Type
Input
Input
Input
Input
Output
Output
Width
3-6
3-6
3-6
3-6
1
1
Signal Description
Parity 3 (systematic) data port 1
Parity 3 (systematic) data port 2
Parity 4 (interleaved) data port 1
Parity 4 (interleaved) data port 2
Write enable for parity 3 (systematic)
Write enable for parity 4 (interleaved)
IPexpress? User-Con?gurable Core
The Turbo Decoder core is an IPexpress User-Con?gurable IP core, which allows designers to con?gure the IP and
generate netlists as well as simulation ?les for use in designs. The IPexpress ?ow also supports a hardware evalu-
ation capability, making it possible to create versions of the IP core that operate in hardware for a limited period of
time without requiring the purchase of an IP license.
To download a full evaluation version of this IP core, please go to the Lattice IP Server tab in the ispLEVER ? IPex-
press GUI window. All ispLeverCORE? IP cores available for download are visible on this tab.
References
The Lattice Turbo Decoder IP core is compliant with two standards: 3GPP and CCSDS. More information about
each standard can be referenced at the following locations.
? The 3rd Generation Partnership Project (www.3gpp.org) provides speci?cations to 3GPP TS 25.212 v4.2.0
(2001-09) standards.
? The Consultative Committee for Space Data Systems (www.ccsds.org) provides speci?cations to CCSDS 101.0-
B-5 standards.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TURBO-DECO-PM-UT3 | 功能描述:开发软件 TURBO DECODER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TURBO-DECO-SC-U3 | 功能描述:开发软件 Turbo Decoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TURBO-DECO-SC-UT3 | 功能描述:开发软件 TURBO DECODER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TURBO-DECO-X2-U3 | 功能描述:开发软件 Turbo Decoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TURBO-DECO-X2-UT3 | 功能描述:开发软件 TURBO DECODER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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