- 您现在的位置：买卖IC网 > PDF目录98305 > TVP5146PFPRG4 (TEXAS INSTRUMENTS INC) COLOR SIGNAL DECODER, PQFP80 PDF资料下载
参数资料
| 型号： | TVP5146PFPRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封装： | PLASTIC, HTQFP-80 |
| 文件页数： | 17/106页 |
| 文件大小： | 1500K |
| 代理商： | TVP5146PFPRG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
10
SLES084C August 2007
TVP5146
2.1.2 Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The
clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference
voltage. The selection between bottom and mid clamp is performed automatically by the
TVP5146 decoder.
2.1.3 Automatic Gain Control
The TVP5146 decoder uses four programmable gain amplifiers (PGAs), one per channel. The
PGA can scale a signal with a voltage-input compliance of 0.5-VPP to 2-VPP to a full-scale 10-bit
A/D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel.
Minimum gain corresponds to a code 0x0 (2-VPP full-scale input, –6-dB gain) while maximum
gain corresponds to code 0xF (0.5 VPP full scale, +6-dB gain). The TVP5146 decoder also has
12-bit fine gain controls for each channel and applies independently to coarse gain controls. For
composite video, the input video signal amplitude can vary significantly from the nominal level of
1 VPP. The TVP5146 decoder can adjust its PGA setting automatically: an AGC can be enabled
and can adjust the signal amplitude such that the maximum range of the ADC is reached without
clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In
these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the
TVP5146 decoder can read the gain currently being used.
The TVP5146 AGC comprises the front-end AGC before Y/C separation and the back-end AGC
after Y/C separation. The back-end AGC restores the optimum system gain whenever an
amplitude reference such as the composite peak (which is only relevant before Y/C separation)
forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms
can use up to four amplitude references: sync height, color burst amplitude, composite peak,
and luma peak.
The specific amplitude references being used by the front-end and back-end AGC algorithms
can be independently controlled using the AGC white peak processing register located at
subaddress 74h. The TVP5146 gain increment speed and gain increment delay can be
controlled using the AGC increment speed register located at subaddress 78h and the AGC
increment delay register located at subaddress 79h, respectively.
2.1.4 Analog-to-Digital Converters (ADCs)
All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive
an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and
30 MHz. All ADC reference voltages are generated internally.
2.2
Digital Video Processing
Figure 22 is a block diagram of the TVP5146 digital video decoder processor. This processor
receives digitized video signals from the ADCs and performs composite processing for CVBS
and S-video inputs, YCbCr signal enhancements for CVBS and S-video inputs, and YPbPr/RGB
processing for component video inputs. It also generates horizontal and vertical syncs and other
output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide
field identification, horizontal and vertical lock, vertical blanking, and active video window
indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with
external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync
pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material.
Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656
output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port
interface.
相关PDF资料 |
PDF描述 |
|---|---|
| TVP5146PFP | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146PFPR | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146PFPG4 | COLOR SIGNAL DECODER, PQFP80 |
| TVP5147M1PFPG4 | COLOR SIGNAL DECODER, PQFP80 |
| TVP5147M1PFPRG4 | COLOR SIGNAL DECODER, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TVP5147EVM | 功能描述:视频 IC 开发工具 TVP5147 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Evaluation Boards 类型:YPbPr to RGBHV Converters 工具用于评估:LMH1251 工作电源电压:5 V |
| TVP5147M1 | 制造商:TI 制造商全称:Texas Instruments 功能描述:NTSC/PAL/SECAM 2x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr Inputs, and 5-Line Comb Felter |
| TVP5147M1_08 | 制造商:TI 制造商全称:Texas Instruments 功能描述:NTSC/PAL/SECAM 2x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr Inputs, and 5-Line Comb Felter |
| TVP5147M1IPFP | 功能描述:视频 IC 10B Hi Qual Sgl-Chip Dig Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| TVP5147M1IPFPR | 功能描述:视频 IC 10B Hi Qual Sgl-Chip Dig Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。