参数资料
型号: TVP5147M1PFPRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP80
封装: PLASTIC, HTQFP-80
文件页数: 17/100页
文件大小: 1369K
代理商: TVP5147M1PFPRG4
Functional Description
15
SLES140A—March 2007
TVP5147M1PFP
2.3
Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drive
the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal
of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2). If a
parallel resonant circuit is used as shown in Figure 210, then the external capacitors must have the following
relationship:
CL1 = CL2 = 2CL CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 210 shows the reference clock
configurations. The TVP5147M1 decoder generates the DATACLK signal used for clocking data.
TVP5147M1
74
XTAL1
14.318-MHz
Crystal
75
XTAL2
TVP5147M1
74
XTAL1
75
XTAL2
CL1
CL2
14.318-MHz
Clock
Figure 210. Reference Clock Configurations
2.4
Real-Time Control (RTC)
Although the TVP5147M1 decoder is a line-locked system, the color burst information is used to determine
accurately the color subcarrier frequency and phase. This ensures proper operation with nonstandard video
signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video
line frequency. The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are
transmitted via terminal 37 (GLCO) for optional use in an end system (for example, by a video encoder). The
frequency control word is a 23-bit binary number. The instantaneous frequency of the color subcarrier can be
calculated using the following equation:
F
PLL +
F
ctrl
223
F
sclk
where FPLL is the frequency of the subcarrier PLL, Fctrl is the 23-bit PLL frequency control word, and Fsclk is
two times the pixel frequency. This information can be generated on the GLCO terminal. Figure 211 shows
the detailed timing diagram.
RTC
45 CLK
18 CLK
L
S
B
0
3 CLK
128 CLK
23-Bit Fsc PLL Increment
Start
Bit
1 CLK
R
S
Invalid
Sample
Valid
Sample
M
S
B
22
Reserved
NOTE:
RTC reset bit (R) is active-low, Sequence bit (S) PAL: 1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change
Figure 211. RTC Timing
2.5
Output Formatter
The output formatter sets how the data is formatted for output on the TVP5147M1 output buses. Table 21
shows the available output modes.
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