参数资料
型号: TVP5150AM1MPBSREP
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP32
封装: PLASTIC, TQFP-32
文件页数: 18/79页
文件大小: 896K
代理商: TVP5150AM1MPBSREP
3.15.2.3 I2C Timing Requirements
3.16 Clock Circuits
TVP5150AM1
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150AM1
5
XTAL1
6
XTAL2
CL1
CL2
14.31818-MHz
TTL Clock
R
3.17 Genlock Control (GLCO) and RTC
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
www.ti.com
SLES213 – MAY 2008
The TVP5150AM1 decoder requires delays in the I2C accesses to accommodate its internal processor's
timing. In accordance with I2C specifications, the TVP5150AM1 decoder holds the I2C clock line (SCL) low
to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock
line held-low condition, then the maximum delays always must be inserted where required. These delays
are of variable length; maximum delays are indicated in the following diagram:
Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays).
Slave
Start
address
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 64
s
Stop
(B8h)
The 64-
s delay is for all registers that do not require a reinitialization. Delays may be more for some
registers.
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to
drive the PLL. This may be input to the TVP5150AM1 decoder on terminal 5 (XTAL1), or a crystal of
14.31818-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2).
Figure 3-5 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have
the following relationship:
CL1 = CL2 = 2CL – CSTRAY
where CSTRAY is the terminal capacitance with respect to ground. Figure 3-5 shows the reference clock
configurations.
A.
R depends on crystal specification and may not be required.
Figure 3-5. Reference Clock Configurations
A Genlock control function is provided to support a standard video encoder to synchronize its internal
color oscillator for properly reproduced color with unstable timebase sources such as VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the
subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit
binary number. The frequency of the DTO can be calculated from the following equation:
Fdto = (Fctrl/2
23)
× F
sclk
where Fdto is the frequency of the DTO, Fctrl is the 23-bit DTO frequency control, and Fsclk is the frequency
of the SCLK.
Functional Description
25
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