参数资料
型号: TVP5151IPBSQ1
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP32
封装: GREEN, PLASTIC, QFP-32
文件页数: 11/86页
文件大小: 964K
代理商: TVP5151IPBSQ1
TVP5151
www.ti.com
SLES241C – SEPTEMBER 2009 – REVISED SEPTEMBER 2010
3.15 I
2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used
for slave address selection. Although the I2C system can be multimastered, the TVP5151 decoder
functions only as a slave device.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is
free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5151
decoders tied to the same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the
write and read addresses to be used for the TVP5151 decoder, it can either be pulled low or high through
a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or
IO_DVDD. Table 3-6 summarizes the terminal functions of the I2C-mode host interface.
Table 3-5. Write Address
Selection
I2CSEL
WRITE ADDRESS
0
B8h
1
BAh
Table 3-6. I2C Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CSEL (YOUT7)
I
Slave address selection
SCL
I/O (open drain)
Input/output clock line
SDA
I/O (open drain)
Input/output data line
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes which can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
Copyright 2009–2010, Texas Instruments Incorporated
Functional Description
19
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