SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
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4.1
I
2C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5154A decoder by generating a start condition (S)
followed by the TVP5154A I2C address (as shown below), in MSB first bit order, followed by a 0 to
indicate a write cycle. After receiving an acknowledge from the TVP5154A decoder, the master presents
the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more
bytes of data, MSB first. The TVP5154A decoder acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition (P).
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
1
0
1
0
X
0
Step 3
9
I2C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C write register address (master)
addr
Step 5
9
I2C acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
I2C write data (master)
Data
Step 7(1)
9
I2C acknowledge (slave)
A
Step 8
0
I2C stop (master)
P
(1)
Repeat steps 6 and 7 until all data have been written.
4.2
I
2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP5154A decoder by generating a start condition (S) followed by
the TVP5154A I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledges from the TVP5154A decoder, the master presents the sub-address of the register or the
first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the
cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the
TVP5154A decoder by generating a start condition followed by the TVP5154A I2C address (as shown
below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an
acknowledge from the TVP5154A decoder, the I2C master receives one or more bytes of data from the
TVP5154A decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data
byte desired has been transferred from the TVP5154A decoder to the master, the master generates a not
acknowledge followed by a stop.
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I2C Host Interface