参数资料
型号: TVP5154PNPR
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP128
封装: GREEN, PLASTIC, HTQFP-128
文件页数: 79/79页
文件大小: 908K
代理商: TVP5154PNPR
www.ti.com
4.7 Timing Processor
4.8 VBI Data Processor
4.9 VBI FIFO and Ancillary Data in Video Stream
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
The timing processor is a combination of hardware and software running in the internal microprocessor
that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the
analog front end, and vertical sync detection.
The TVP5154 VBI data processor (VDP) slices various data services, such as teletext (WST, NABTS),
closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the
VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results
are stored in a FIFO only. Table 4-1 lists a summary of the types of VBI data supported according to the
video standard. It supports ITU-R BT. 601 sampling for each.
Table 4-1. Data Types Supported by the VDP
LINE MODE REGISTER
NAME
DESCRIPTION
(D0h–FCh) BITS [3:0]
0000b
WST SECAM
Teletext, SECAM
0001b
WST PAL B
Teletext, PAL, System B
0010b
WST PAL C
Teletext, PAL, System C
0011b
WST, NTSC B
Teletext, NTSC, System B
0100b
NABTS, NTSC C
Teletext, NTSC, System C
0101b
NABTS, NTSC D
Teletext, NTSC, System D (Japan)
0110b
CC, PAL
Closed caption PAL
0111b
CC, NTSC
Closed caption NTSC
1000b
WSS, PAL
Wide-screen signal, PAL
1001b
WSS, NTSC
Wide-screen signal, NTSC
1010b
VITC, PAL
Vertical interval timecode, PAL
1011b
VITC, NTSC
Vertical interval timecode, NTSC
1100b
VPS, PAL
Video program system, PAL
1111b
Active Video
Active video/full field
At power up, the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents
with the lookup table (see Section 9.2.63). This is done through port address C3h. Each read from or write
to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM,
the line mode registers (D0h–FCh) must be programmed with FFh to avoid a conflict with the internal
microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h–AFh,
both of which are available through the I2C port.
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is
output during the horizontal blanking period following the line from which the data was retrieved. Table 4-2
shows the header format and sequence of the ancillary data inserted into the video stream. This format is
also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can
store up to 11 lines of teletext data with the NTSC NABTS standard.
Functional Description
9
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