SLES243E
– JULY 2009 – REVISED MARCH 2011
3.1.2
Analog Video Input Clamping
An internal clamping circuit provides dc restoration for all four analog composite video inputs. The dc
restoration circuit (sync-tip clamp) restores sync-tip level of the ac-coupled composite video signal to a
fixed dc level near the bottom of the A/D converter range.
3.1.3
A/D Converter
All ADCs have a resolution of 10 bits and can operate at 27 MSPS. Each A/D channel receives a clock
from the on-chip phase-locked loop (PLL) at a nominal frequency of 27 MHz. All ADC reference voltages
are generated internally.
3.2
Digital Video Processing
Digital Video Processing block receives digitized video signals from the ADCs and performs composite
processing and YCbCr signal enhancements. The digital data output can be programmed to two formats:
ITU-R BT.656 8-bit 4:2:2 with embedded syncs or 16-bit 4:2:2 with embedded syncs. The circuit also
detects pseudo-sync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected
material.
3.2.1
2x Decimation Filter
All input signals are over-sampled by a factor of 2 (by 27-MHz clock). The A/D outputs initially pass
through decimation filters that reduce the data rate to 1x the pixel rate. The decimation filter is a half-band
filter. Over-sampling and decimation filtering can effectively increase the overall signal-to-noise ratio by
3 dB.
3.2.2
Automatic Gain Control
The automatic gain control (AGC) can be enabled and can adjust the signal amplitude controlled by 14-bit
digital gain stage after the ADC. The AGC algorithms can use up to four amplitude references: sync
height, color burst amplitude, composite peak, and luma peak.
The specific amplitude references being used by the AGC algorithms can be controlled using the AGC
white peak processing register located at sub-address 2Dh. The gain increment speed and gain increment
delay can be controlled using the AGC increment speed register located at sub-address 29h and the AGC
increment delay register located at sub-address 2Ah. The gain decrement speed and gain decrement
delay can be controlled using the AGC decrement speed register located at sub-address 2Bh and the
AGC decrement delay register located at sub-address 2Ch.
3.2.3
Composite Processor
This Composite Processor circuit receives a digitized composite signal from the ADCs and performs sync
and Y/C separation, chroma demodulation for PAL/NTSC, and YUV signal enhancements. The slice levels
of the sync separator are adaptive. The slice levels continually adapt to changes in the back-porch and
sync-tip levels. The 10-bit composite video is multiplied by the sub carrier signals in the quadrature
demodulator to generate U and V color difference signals. The U and V signals are then sent to low-pass
filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the
unique property of color phase shifts from line to line. The chroma is re-modulated through a quadrature
modulator and subtracted from line-delayed composite video to generate luma. This form of Y/C
separation is completely complementary, thus there is no loss of information. However, in some
applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be
turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path.
Contrast, brightness, sharpness, hue, and saturation controls are programmable through the I2C host port.
Figure 3-3 shows the block diagram of Composite Processor.
Copyright
2009–2011, Texas Instruments Incorporated
Functional Description
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