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参数资料
| 型号： | U3900BM-AFNG3 |
| 英文描述： | Programmable Telephone Audio Processor |
| 中文描述： | 程控电话音频处理器 |
| 文件页数： | 31/34页 |
| 文件大小： | 762K |
| 代理商： | U3900BM-AFNG3 |
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U3900BM
Rev. A2, 25-Aug-98
Target Specification
6 (34)
2.1.5
Data Recovery and Buffer
The incoming serial data are stored and sent to the SSB
each 10 bits (1 start bit, 8 data, 1 stop bit ). When after a
start bit 8 data bits and a stop bit are received, an interrupt
is generated, the INT pin will become active, and data
ready interrupt bit is set in the status register (bit 3). The
received data is available in the CLID DATA register.
14605
DATA
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
INT pin
Figure 3. Interrupt treatment for SLID DATA register
2.1.6
CLID: Logical Part
14606
Data recovery
and
buffer
NCD
DATA
DR
CD
Serial
data
Data ready
Clock
Demodulator
Carrier
detect
Command bits
CD_CD < 3...0 >
from serial bus
Command bit SCD
from serial bus
FSK
signal
From/to
demodulator analog filter
Clock
recovery
Figure 4. Block diagram for CLID logical part
2.1.7
Carrier Detect, Bandpass Frequencies
Low Frequencies
CD_CD<0>
CD_CD<1>
Value
0
290 Hz
1
0
515 Hz
0
1
770 Hz
1
1000 Hz
High Frequencies
CD_CD<2>
CD_CD<3>
Value
0
3400 Hz
1
0
3100 Hz
0
1
2665 Hz
1
1700 Hz
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