参数资料
型号: UBA2014P/N1,112
厂商: NXP Semiconductors
文件页数: 5/19页
文件大小: 0K
描述: IC CNTL BALLAST 600V 16-DIP
标准包装: 1,000
类型: 镇流器控制器
频率: 40.5 ~ 100 kHz
电流 - 电源: 1.5mA
电流 - 输出: 330mA
电源电压: 9.1 V ~ 13 V
工作温度: -25°C ~ 80°C
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-DIP
包装: 管件
其它名称: 568-3321-5
935270383112
UBA2014P/N1
NXP Semiconductors
UBA2014
600 V driver IV for HF ?uorescent lamps
8. Functional description
8.1 Start-up state
Initial start-up can be achieved by charging the low-voltage supply capacitor C7
(see Figure 8 ) via an external start-up resistor. Start-up of the circuit is achieved under the
condition that both half bridge transistors TR1 and TR2 are non-conductive. The circuit
will be reset in the start-up state. If the low-voltage supply (V DD ) reaches the value of
V DD(start) the circuit will start oscillating. A DC reset circuit is incorporated in the High-Side
(HS) driver. Below the lockout voltage at the FV DD pin the output voltage (V GH ? V SH ) is
zero. The voltages at pins CF and CT are zero during the start-up state.
8.2 Oscillation
The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the V CF(high) level and 0 V. The frequency of the sawtooth is
determined by capacitor C CF , resistor R IREF , and the voltage at pin CSW. The minimum
and maximum switching frequencies are determined by R IREF and C CF ; their ratio is
internally ?xed. The sawtooth frequency is twice the half bridge frequency. The UBA2014
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is illustrated in
Figure 4 . The oscillator starts oscillating at f max . During the ?rst switching cycle the
Low-Side (LS) transistor is switched on. The ?rst conducting time is made extra long to
enable the bootstrap capacitor to charge.
8.3 Adaptive non-overlap
The non-overlap time is realized with an Adaptive Non-overlap circuiT (ANT). By using an
adaptive non-overlap circuit, the application can determine the duration of the non-overlap
time and make it optimum for each frequency; see Figure 4 . The non-overlap time is
determined by the slope of the half bridge voltage, and is detected by the signal across
resistor R16 which is connected directly to pin ACM. The minimum non-overlap time is
internally ?xed. The maximum non-overlap time is internally ?xed at approximately 25 %
of the bridge period time. An internal ?lter of 30 ns is included at the ACM pin to increase
the noise immunity.
8.4 Timing circuit
A timing circuit is included to determine the preheat time and the ignition time. The circuit
consists of a clock generator and a counter.
The preheat time is de?ned by C CT and R IREF and consists of 7 pulses at C CT ; the
maximum ignition time is 1 pulse at C CT . The timing circuit starts operating after the
start-up state, as soon as the low supply voltage (V DD ) has reached V DD(start) or when a
critical value of the lamp voltage (V lamp(fail) ) is exceeded. When the timer is not operating
C CT is discharged to 0 V at 1 mA.
UBA2014_4
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 16 October 2008
5 of 19
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