参数资料
| 型号： | UBA2036TS/N1,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 5/13页 |
| 文件大小： | 0K |
| 描述： | IC DVR FULL BRIDGE 28-SSOP |
| 标准包装： | 1,000 |
| 类型： | HID 灯控制器 |
| 频率： | 100kHz |
| 电流 - 电源： | 500µA |
| 电流 - 输出： | 200mA |
| 电源电压： | 10.5 V ~ 13.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 935284159118 |
NXP Semiconductors
UBA2036TS
Full bridge control IC for HID automotive lighting
Table 3. Driver …continued
Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK.
Device
BD SU DD
CLK
GHL
GHR
GLL
GLR
state
Oscillation
state
1
0
0
0
-
0
1
1
-
-
1
1
-
-
1
0
0 (= V SHL )
0 (= V SHL )
0 (= V SHL )
1 (= V FSL )
0 (= V SHR )
0 (= V SHR )
1 (= V FSR )
0 (= V SHR )
0 (= V PGND )
1 (= V VDD )
1 (= V VDD )
0 (= V PGND )
0 (= V PGND )
1 (= V VDD )
0 (= V PGND )
1 (= V VDD )
0
1
0 [1]
1 →
0 [2]
GHL
GHR
GLL
GLR
[1]
[2]
If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the pre-de?ned
position: V GHL = V FSL , V GLR = V VDD , V GLL = V PGND , and V GHR = V SHR .
Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR
changes.
If there is no external clock available, the internal oscillator can be used. The design
K osc × R osc × C osc
1
f bridge = ---------------------------------------------
(1)
R osc and C osc are external components connected to the RC pin (R osc connected to pin
VDD and C osc connected to pin SGND). In this situation the pins V DD(CLK) , CLK and
V SS(CLK) can be connected to SGND.
The clock signal, coming from either pin RC or pin CLK, is divided by two in order to obtain
a 50 % duty-cycle gate drive signal. This can be achieved by applying a voltage to the DD
input lower than V IL(DD) (e.g. connect pin DD to pin SGND).
7.4 Non-overlap time
In the full bridge con?guration the non-overlap time is de?ned as the time between turning
off the two conducting MOSFETs and turning on the two other MOSFETs. The
non-overlap time is realized by means of an adaptive non-overlap circuit. With an adaptive
non-overlap, the application determines the duration of the non-overlap and makes the
non-overlap time optimal for each frequency. The non-overlap time is determined by the
duration of the falling slope of the relevant half bridge voltage. The occurrence of a slope
is sensed internally. The minimum non-overlap time is internally ?xed.
7.5 Start-up delay
A simple resistor-capacitor (RC) ?lter (R between pin VDD and pin SU; C between pin SU
and pin SGND) or a control signal from a processor can be used to make a start-up delay.
This can be bene?cial for those applications in which building up the high voltage takes a
larger amount of time: A start-up delay will ensure that the HID system will not start up
before this high voltage has been reached.
7.6 Bridge disable
The bridge disable function can be used to switch off all the MOSFETs as soon as the
voltage on pin BD exceeds the bridge disable voltage V BD . The bridge disable function
overrules all the other states.
UBA2036TS_1
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 30 October 2008
5 of 13
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