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参数资料
| 型号： | UC1886J |
| 元件分类： | 稳压器 |
| 英文描述： | 1.5 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, CDIP16 |
| 文件页数： | 4/7页 |
| 文件大小： | 278K |
| 代理商： | UC1886J |
4
UC1886
UC2886
UC3886
BUF: (Buffer Output) The voltage on COMMAND pin is
buffered and presented to the user here. This voltage is
used to provide the operating bias point for the current
sense amplifier by connecting a resistor between BUF
and ISP. Decouple BUF with 0.01
F or greater to SGND.
CAM: (Current Amplifier Minus Input) The average load
current feedback from ISO is typically applied through a
resistor here.
CAO/ENBL: (Current Amplifier Output/Chip Enable) The
current loop compensation network is connected be-
tween CAO/ENBL and CAM, the inverting input of the
current amplifier. The voltage at CAO/ENBL is the input
to the PWM comparator and regulates the output voltage
of the system. The GATE output is disabled (held low)
unless the voltage at this pin exceeds 1.0 volts, allowing
the PWM to force zero duty cycle when necessary. The
user can force this pin below 0.8 volts externally with an
open collector, disabling the GATE drive.
COMMAND: (Voltage Amplifier Non-Inverting Input) This
input to the voltage amplifier is connected to a command
voltage, such as the output of a DAC. This voltage sets
the switching regulator output voltage.
COMP: (Compensation, Voltage Amplifier Output) The
system voltage compensation network is applied be-
tween COMP and VSENSE. The voltage at COMP is
clamped to prevent it from going more than 1V above the
COMMAND voltage. This is used to provide an accurate
average current limit. The voltage on COMP is also
clamped to 0.7V below the voltage on COMMAND. This
is done to avoid applying a full charge to capacitors in
the compensation network during transients, allowing
quick recovery time and little overshoot.
CT: (Oscillator Timing Capacitor) A capacitor from CT to
SGND along with the resistor on RT, sets the PWM fre-
quency and maximum duty cycle according to these
formulas:
D
V
RT
mA
MAX =
1
20
40
.
where DMAX is the maximum operating duty cycle, and
RT is in ohms.
()
F
VmA RT
V
CT
V RT
mA
OSC =
20
40
20
18
4 0
..
.
..
where FOSC is the UC3886 oscillator switching fre-
quency in Hz, RT is in ohms, and CT is in farads.
GATE: (PWM Output) The output is a 1A totem pole
driver. Use a series resistor of at least 5
to prevent in-
teraction between the gate impedance and the output
driver that might cause excessive overshoot.
ISN: (Current Sense Amplifier Inverting Input) A resistor
to the low side of the average current sense resistor and
a resistor to ISO are applied to this pin to make a differ-
ential sensing amplifier.
ISO: (Current Sense Amplifier Output) A feedback resis-
tor to ISN is connected here to make a differential
sensing amplifier. The voltage at this pin is equal to
(VBUF +AIAVG RSENSE) where A is the user deter-
mined gain of the differential amplifier, IAVG is the
average load current of the system, and RSENSE is the
average current sensing resistor. For stability, A must be
greater than 5. Set A such thatAISC RSENSE = 1.0V
where ISC is the user-determined short circuit current
limit.
ISP: (Current Sense Amplifier Non-Inverting Input) A re-
sistor to the high side of the average current sense
resistor and a resistor to BUF are connected to this pin
to make a differential sensing amplifier.
PGND: (Power Ground) The PWM output current returns
to ground through this pin. This is separated from SGND
to avoid on-chip ground noise generated by the output
current.
RT: (Oscillator Charging Current) This pin is held at 2V.
Resistor RT from this pin to SGND sets the oscillator
charging current. Use 5k < RT < 100k.
SGND: (Signal Ground) For better noise immunity, sig-
nal ground is provided at this pin.
VCC: (Positive Supply Voltage) This pin supplies power
to the chip and to the gate drive output. Decouple to
PGND and separately to SGND for best noise immunity.
The reference (VREF), GATE output, oscillator, and am-
plifiers are disabled until VCC exceeds 10.3V.
VREF: (Voltage Reference Output) An accurate 5V refer-
ence as provided at this pin. The output can deliver 2mA
to external circuitry, and is internally short circuit current
limited. VREF is disabled if VCC is below UVLO. Bypass
5V REF to SGND with an 0.01
F or larger capacitor for
best stability.
VSENSE: (Voltage Sense Input) This input is connected
to COMP through a feedback network and to the power
supply output through a resistor or a divider network.
PIN DESCRIPTIONS
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