参数资料
型号: UCC28051P
厂商: Texas Instruments
文件页数: 9/32页
文件大小: 0K
描述: IC PFC CTRLR TRANSITION 8DIP
标准包装: 50
模式: 间歇(跃迁)
频率 - 开关: 200kHz
电流 - 启动: 75µA
电源电压: 12 V ~ 18 V
工作温度: -40°C ~ 105°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1052 (CN2011-ZH PDF)
配用: 296-19036-ND - EVAL MODULE FOR UCC28051
其它名称: 296-15224-5
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F?SEPTEMBER 2002 ? REVISED MARCH 2009
BLOCK DESCRIPTION (continued)
Zero Power Block
When the output of the g M amplifier goes below 2.3 V, the zero power comparator latches the gate drive signal
low. The slew rate enhancement circuitry of the g M amplifier that is activated during overvoltage conditions slews
the COMP pin to about 2.4 V. This ensures that the zero power comparator is not activated during transient
behavior (when the slew rate enhancement circuitry is enhanced).
Multiplier Block
The multiplier block has two inputs. One is the error amplifier output voltage (V COMP ), while the other is V MULTIN
which is obtained by a resistive divider from the rectified line. The multiplier output is approximately
0.67 × V MULTIN × (V COMP ?2.5 V). There is a positive offset of about 75 mV to the V MULTIN signal because this
improves the zero-crossing distortion and hence the THD performance of the controller in the application. The
dynamic range of the inputs can be found in the electrical characteristics table.
Overvoltage Protection (OVP) Block
The OVP feature in the part is not activated under most operating conditions because of the presence of the
slew rate enhancement circuitry present in the error amplifier. As soon as the output voltage reaches to about
5% to 7% above the nominal value, the slew rate enhancement circuit is activated and the error amplifier output
voltage is pulled below the dynamic range of the multiplier block. This prevents further rise in output voltage.
If the COMP pin is not pulled low fast enough, and the voltage rises further, the OVP circuit acts as a second
line of protection. When the voltage at the VO_SNS pin is more than 7.5% of the nominal value
( >(V REF +0.190)), the OVP feature is activated. It stops the gate drive from switching as long as the voltage at
the VO_SNS pin is above the nominal value (V REF ). This prevents the output dc voltage from going above 7.5%
of the nominal value designed for, and protects the switch and other components of the system like the boost
capacitor.
Transition Mode Control
The boost converter, the most common topology used for power factor correction, can operate in two modes
– continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also
referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the
boundary between CCM and DCM by adjusting the switching frequency.
The CRM converter typically uses a variation of hysteretic control with the lower boundary equal to zero current.
It is a variable frequency control technique that has inherently stable input current control while eliminating
reverse recovery rectifier losses. As shown in Figure 1, the switch current is compared to the reference signal
(output of the multiplier) directly. This control method has the advantage of simple implementation and still can
provide very good power factor correction.
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