参数资料
型号: UCC3957M-3G4
厂商: Texas Instruments
文件页数: 9/15页
文件大小: 0K
描述: IC L-I PROTECTOR CIRCUIT 16-QSOP
标准包装: 75
功能: 过压/欠压保护
电池化学: 锂离子(Li-Ion)
电源电压: 5 V ~ 20 V
工作温度: -20°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP/QSOP
包装: 管件
Not Recommended for New Designs
UCC3957 1, UCC3957 2, UCC3957 3, UCC3957 4
SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
protecting against inductive kick at turn-off
In the case of a short circuit, the di/dt that occurs when the discharge FET is turned off can result in a significant
voltage undershoot at the pack output due to stray inductance. This undershoot can potentially exceed the
breakdown voltage rating of the discharge FET. A clamp diode (D1 in Figure 1, Figure 2, and Figure 3), or a
capacitor across the pack output, protects against this possibility. A diode also provides protection from a
reverse-polarity charger.
During turn-off, a voltage overshoot can occur at the top of the cell stack, due to wiring inductance and the cells ’
internal equivalent series inductance (ESL). During very high di/dt conditions, such as occurs when turning off
in response to a short circuit, this voltage overshoot can be significant and potentially damage the IC or the
discharge FET (Q2). For this reason, it is strongly recommended that a capacitor (C5) be placed across the cell
stack, from VDD to AN4, and that stray inductance be minimized in the battery-current path. Additional methods
to reduce di/dt across the cell stack are discussed in the following section.
controlling discharge FET turn-on and turn-off times
Slew-rate limiting the pack output voltage at turn-on greatly reduces the surge current into large capacitive
loads.
This allows the designer to select shorter overcurrent-delay times, minimizing the stress on Q1 and Q2 in the
event of a shorted pack output. A simple method of implementing slew-rate limiting is shown in Figure 3. It
consists of an RC network (R3 and C6) between gate and drain of the discharge FET (Q2) to control its turn-on
time. This circuit relies on the relatively high-sink impedance (about 20 k ? ) of the UCC3957 ’ s DCHG output.
The values shown for R3 and C6 provide a pack output voltage rise time of about 4.5 ms when the discharge
FET (Q2) is turned on. Note that the addition of R3 and C6 has made it possible to eliminate the CDLY2
capacitor, for the quickest response to a true short circuit. While this circuit does not prevent a large surge current
when inserting a live battery pack into a highly-capacitive load, it does allow it to restart (after one hiccup cycle)
if this initial surge-current trips the overcurrent protection.
Increasing the turn-off time of the discharge FET (Q2) reduces the inductive kick that results during turn-off after
an overcurrent condition. This is accomplished by adding a resistor (R4) in series with the DCHG output. This
reduction of di/dt at turn-off minimizes the need for a capacitor across the battery stack. It is recommended that
this resistor value not exceed a few hundred Ohms, in which case the ability to turn off quickly enough into a
short may be compromised.
Due to the relatively low-charge currents (typically a few Amperes max), controlling the turn-on and turn-off
times of the charge FET is not beneficial. In fact, the turn-off time of the charge FET is slow due to the large value
of R1, the gate-to-source resistor.
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