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参数资料
| 型号： | UDA1330ATS/N2,118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | DAC |
| 英文描述： | Low-cost stereo filter DAC; Package: SOT369-1 (SSOP16); Container: Reel Pack, SMD, 13" |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封装： | PLASTIC, MO-152, SOT369-1, SSOP-16 |
| 文件页数： | 9/13页 |
| 文件大小： | 164K |
| 代理商： | UDA1330ATS/N2,118 |
2001 Feb 02
5
NXP Semiconductors
Product specification
Low-cost stereo filter DAC
UDA1330ATS
FUNCTIONAL DESCRIPTION
System clock
The UDA1330ATS operates in slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (fsys) is
selectable and depends on the application mode. The
options are: 256fs,384fs and 512fs for the L3 mode and
256fs or 384fs for the static pin mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1330ATS supports sampling frequencies from
8to55kHz.
Application modes
The application mode can be set with the three-level
pin APPSEL (see Table 1):
L3 mode
Static pin mode with f
sys =384fs
Static pin mode with f
sys =256fs.
Table 1
Selecting application mode and system clock
frequency via pin APPSEL
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
Table 2
Functions of application input pins
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.
Multiple format input interface
DATA FORMATS
The digital interface of the UDA1330ATS supports multiple
format inputs (see Fig.3).
Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all
LSB-justified formats.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS.
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.
The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes
L3 MODE
This mode supports the following input formats:
I2S-bus format with data word length of up to 20 bits
MSB-justified format with data word length up to 20 bits
LSB-justified format with data word length of
16, 18 or 20 bits.
STATIC PIN MODE
This mode supports the following input formats:
I2S-bus format with data word length of up to 20 bits
LSB-justified format with data word length of
16, 18 or 20 bits.
These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).
Table 3
Input format selection using SF0 and SF1
VOLTAGE ON
PIN APPSEL
MODE
fsys
VSSD
L3 mode
256fs,384fs or 512fs
0.5VDDD
static pin mode
384fs
VDDD
256fs
PIN
FUNCTION
L3 MODE
STATIC PIN MODE
APPL0
TEST
MUTE
APPL1
L3CLOCK
DEEM
APPL2
L3MODE
SF0
APPL3
L3DATA
SF1
FORMAT
SF0
SF1
I2S-bus
0
LSB-justified 16 bits
0
1
LSB-justified 18 bits
1
0
LSB-justified 20 bits
1
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