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参数资料
| 型号： | UDA1345TS/N2,112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Economy audio CODEC; Package: SOT341-1 (SSOP28); Container: Tube |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | 5.30 MM, PLASTIC, SSOP-28 |
| 文件页数： | 8/28页 |
| 文件大小： | 136K |
| 代理商： | UDA1345TS/N2,112 |
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2002 May 28
16
Philips Semiconductors
Product specication
Economy audio CODEC
UDA1345TS
7.12.2.2
System clock frequency
A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 15).
Table 15 System clock frequency settings
7.12.2.3
Data input format
A 3-bit value (IF2 to IF0) to select the used data format
(see Table 16).
Table 16 Data input format settings
7.12.2.4
DC lter
A 1-bit value to enable the digital DC filter (see Table 17).
Table 17 DC ltering
7.12.2.5
Volume control
A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to
∞ dB in
steps of 1 dB (see Table 18).
Table 18 Volume settings
7.12.2.6
De-emphasis
A 2-bit value to enable the digital de-emphasis filter.
Table 19 De-emphasis settings
7.12.2.7
Mute
A 1-bit value to enable the digital DAC mute (playback).
Table 20 DAC mute
SC1
SC0
FUNCTION
0
512fs
0
1
384fs
1
0
256fs
1
not used
IF2
IF1
IF0
FUNCTION
000
I2S-bus
0
1
LSB-justied; 16 bits
0
1
0
LSB-justied; 18 bits
0
1
LSB-justied; 20 bits
1
0
MSB-justied
1
0
1
MSB-justied output/
LSB-justied 16 bits input
1
0
MSB-justied output/
LSB-justied 18 bits input
1
MSB-justied output/
LSB-justied 20 bits input
DC
FUNCTION
0
no DC ltering
1
DC ltering
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
000000
0
000001
0
000010
1
000011
2
::::::
:
110011
50
110100
52
110001
54
110010
57
110111
60
111000
66
111001
∞
::::::
:
111111
∞
DE1
DE0
FUNCTION
0
no de-emphasis
0
1
de-emphasis; 32 kHz
1
0
de-emphasis; 44.1 kHz
1
de-emphasis; 48 kHz
MT
FUNCTION
0
no muting
1
muting
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