参数资料
型号: UPB1007K-E1-A
厂商: CEL
文件页数: 5/28页
文件大小: 0K
描述: IC DOWNCONVERT DL 3V 36-QFN
产品变化通告: Product Obsolescence 25/Oct/2011
标准包装: 2,500
RF 型: GPS
频率: 1575.42MHz
混频器数目: 2
增益: 15.5dB
噪音数据: 3.2dB
次要属性: 降频变频器
电流 - 电源: 35mA
电源电压: 2.7 V ~ 3.3 V
包装: 带卷 (TR)
封装/外壳: 36-VFQFN
供应商设备封装: 36-QFN(6x6)
μ PB1007K
Pin
Pin Name
Applied
Pin
Function and Application
Internal Equivalent Circuit
No.
Voltage
(V)
Voltage
(V)
9
V CC (PLL Block)
2.7 to 3.3
?
Supply voltage pin of PLL block.
This pin should be externally
12
9
equipped with bypass capacitor to
minimize ground impedance.
10
CP out
?
Output in
Output pin of charge-pump.
accordance This pin should be equipped with
PD
CP
10
with phase external RC in order to adjust
difference.
dumping factor and cut-off
frequency. This tuning voltage
output must be connected to
varactor diode of 1stLO-OSC.
21
11
11
12
GND(PLL Block)
V CC (PLL Block)
0
2.7 to 3.3
?
?
Ground pin of PLL block.
Supply voltage pin of PLL block.
This pin should be externally
equipped with bypass capacitor to
minimize ground impedance.
13
LO out
?
1.85
Monitor pin of 1/200 prescaler
output.
IF-MIX PD
PD
14
REF out 2
?
1.68
Monitor pin of 1/2 prescaler
12
15
Power Down1
0 or V CC
?
output.
Stand-by mode control pin of Pre-
amplifier block, 1stLO-OSC block,
1st
LO- ÷25
OSC
÷8
14
13
÷2
Ref.
charge pump prescaler block, LO
output amplifier, RF mixer, IF
mixer, 2ndIF amplifier.
21
Low
High
OFF
ON
Data Sheet PU10014EJ02V0DS
5
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