UPD65806-QFP160P1.2SQ PDF资料下载(11/64 页)ASIC

参数资料

PD64A, 65

Data Sheet U14380EJ2V0DS00

Figure 2-4. Data Memory Organization

→

DP (refer to

2.6 Data Pointer (DP)

)

→

ASR (refer to

2.3 Address Stack Register (ASR (RF))

)

(high-order 4 bits) R

(low-order 4 bits)

2.6 Data Pointer (DP): 11 Bits

The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.

The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 3 bits by

bits 4, 5, and 6 of the P3 register (CR0).

When reset, the pointer contents become “000H”.

Figure 2-5. Data Pointer Organization

Note

Set DP

of the

PD64A to "0".

2.7 Accumulator (A): 4 Bits

The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various

operations.

When reset, the accumulator contents are left undefined.

Figure 2-6. Accumulator Organization

Note

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