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参数资料
| 型号： | UPD70F3038F1-EN2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PBGA180 |
| 封装： | 13 X 13 MM, PLASTIC, FBGA-180 |
| 文件页数： | 19/26页 |
| 文件大小： | 760K |
| 代理商： | UPD70F3038F1-EN2 |
Data Sheet U14622EJ2V1DS
26
PD70F3038, 70F3038Y, 70F3040, 70F3040Y
(2) 20 MHz operation
(TA = –40 to +85°C, VDD = AVDD = BVDD = 3.1 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
Pins in Note 1, WAIT
0.7 BVDD
BVDD
V
VIH2
Pins in Note 2
0.7 VDD
VDD
V
VIH3
Pins in Note 3, RESET
0.75 VDD
VDD
V
VIH4
Pins in Note 4
0.7 AVDD
AVDD
V
Input voltage, high
VIH5
X1
0.8 VDD
VDD
V
VIL1
Pins in Note 1, WAIT
BVSS
0.3 BVDD
V
VIL2
Pins in Note 2
VSS
0.3 VDD
V
VIL3
Pins in Note 3, RESET
VSS
0.2 VDD
V
VIL4
Pins in Note 4
AVSS
0.3 AVDD
V
Input voltage, low
VIL5
X1
VSS
0.2 VDD
V
VPP supply voltage
VPP1
Normal operation
0
0.2 VDD
V
VOH1
Note 1, CLKOUT
IOH =
3 mA
0.8 BVDD
V
Output voltage, high
VOH2
Notes 2, 3
IOH =
1 mA
0.8 VDD
V
VOL1
Note 1, CLKOUT
IOL = 1.6 mA
0.4
V
VOL2
Notes 2, 3 (excluding
P10, P12, P20, P22)
IOL = 1.6 mA
0.4
V
Output voltage, low
VOL3
P10, P12, P20, P22
IOL = 3 mA
0.4
V
ILIH1
Other than X1
5
A
Input
leakage
current,
high
ILIH2
VI = VDD = AVDD =
BVDD
X1
20
A
ILIL1
Other than X1
5
A
Input leakage current, low
ILIL2
VI = 0 V
X1
20
A
Output leakage current,
high
ILOH
VO = VDD = AVDD = BVDD
5
A
Output leakage current,
ILOL
VO = 0 V
5
A
IDD1
Normal operation (fXX = 20 MHz)
45
64
mA
IDD2
HALT mode (fXX = 20 MHz)
20
35
mA
IDD3
IDLE mode (fXX = 20 MHz)
6.5
10
mA
STOP mode (subclock operation: fXT =
32.768 kHz, watch timer operation)
13
115
A
Supply current
IDD4
STOP mode (subclock stopped, XT1 = VSS)
5
100
A
Pull-up resistor
RL
VIN = 0 V
10
30
100
k
Notes 1. Ports 4, 5, 6, and 9 (includes alternate function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,
P150 to P157, P160 to P163, P165 to P167, P180 to P187, and P190 to P197 (includes alternate function
pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, and P170 to P177 (includes alternate function pins)
5. Ports 7 and 8 (includes alternate function pins)
Caution The TYP. value of VDD is 3.3 V. The current that is consumed at output buffers is not included.
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相关代理商/技术参数 |
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| UPD70F3038Y | 制造商:未知厂家 制造商全称:未知厂家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
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