CHAPTER 1 INTRODUCTION
Preliminary User’s Manual U16896EJ1V0UD
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1.2 Features
Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz)
General-purpose registers: 32 bits
× 32 registers
CPU features:
Signed multiplication (16
× 16 → 32): 1 to 2 clocks
(Instructions without creating register hazards can be continuously executed in parallel)
Saturated operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Memory space:
64 MB of linear address space
Internal memory
PD703302, 703302Y (Mask ROM: 128 KB/RAM: 4 KB)
PD70F3302, 70F3302Y (Single-power flash memory: 128 KB/RAM: 4 KB)
Interrupts and exceptions
Non-maskable interrupts: 3 sources
Maskable interrupts:
32 sources (
PD703302, 70F3302)
33 sources (
PD703302Y, 70F3302Y)
Software exceptions:
32 sources
Exception trap:
1 source
I/O lines:
Total: 51
Key interrupt function
Timer function
16-bit timer/event counter P: 1 channel
16-bit timer/event counter 0: 1 channel
8-bit timer/event counter 5:
2 channels
8-bit timer H:
2 channels
8-bit interval timer BRG:
1 channel
Watch timer/interval timer:
1 channel
Watchdog timers
Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel
Watchdog timer 2:
1 channel
Serial interface
Asynchronous serial interface (UART) (supporting LIN): 1 channel
Asynchronous serial interface (UART):
1 channel
3-wire serial I/O (CSI0):
2 channels
I
2C bus interface (I2C):
1 channel
(
PD703302Y, 70F3302Y)
A/D converter: 10-bit resolution
× 8 channels
Real-time output port: 6 bits
× 1 channel
Standby functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes, ring clock operation/ring HALT modes
ROM correction: 4 correction addresses specifiable
Clock generator
Main clock oscillation (fX)/subclock oscillation (fXT)/Ring-OSC (fR)
CPU clock (fCPU) 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode selectable
Ring-OSC: 240 kHz (TYP.)