APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
831
(7/33)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
External main
system clock
Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A)
GRADE PRODUCTS)).
p.165
Be sure to clear bits 1 and 6 of PER0 register to 0.
p.166
Controlling
high-speed
system
clock
High-speed
system clock
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition,
stop peripheral hardware that is operating on the high-speed system clock.
p.167
If switching the CPU/peripheral hardware clock from the high-speed system clock to
the internal high-speed oscillation clock after restarting the internal high-speed
oscillation clock, do so after 10
μs or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
for 10
μs.
p.168
Controlling
internal
high-speed
oscillation
clock
Internal high-
speed oscillation
clock
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation
clock.
p.169
Soft
XT1/P123,
XT2/P124
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
p.169
Hard
When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied
to
the
peripheral
hardware
(except
the
real-time
counter,
clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D
converter and IIC0 are not guaranteed.
For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
well
as
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
pp.169,
170
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
p.169
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
p.170
Subsystem
clock
control
Subsystem clock
The subsystem clock oscillation cannot be stopped using the STOP instruction.
p.170
pp.173,
Chapter
5
Soft
CPU clock
status
transition
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
174, 176
TCR0n:
Timer/counter
register 0n
The count value is not captured to TDR0n even when TCR0n is read.
p.185
TDR0n: Timer
data register 0n
TDR0n does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
p.187
When setting the timer array unit, be sure to set TAU0EN = 1 first. If TAU0EN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values (except for timer input select register 0 (TIS0), input switch control
register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4
(PM0, PM1, PM3, PM4), and port registers 0, 1, 3, 4 (P0, P1, P3, P4)).
p.189
Chapter
6
Soft
Timer
array unit
PER0:
Peripheral
enable register 0
Be sure to clear bit 1, 6 of the PER0 register to 0.
p.189