APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
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(4/35)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
P142/SCK20/
SCL20,
P143/SI20/RxD2
/SDA20,
P144/SO20/
TxD2
To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a
general-purpose port, note the serial array unit 1 setting. For details, refer to the
following tables.
Table 13-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 1:
CSI20, UART2 Transmission, IIC20)
Table 13-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 1:
CSI21, UART2 Reception, IIC21)
p.157
P145/TI07/TO07
To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output
register 0 (TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
p.157
Soft
P140/PCLBUZ0/
INTP6,
P141/PCLBUZ1/
INTP7
To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port,
set bit 7 of clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the
same as their default status settings.
p.157
Hard
Port 15
See 2.2.17 AVREF0 for the voltage to be applied to the AVREF0 pin when using port 15
as a digital I/O.
p.161
P160/TI10/TO10
to
P163/TI13/TO13
To use P160/TI10/TO10 to P163/TI13/TO13 as a general-purpose port, set bits 0 to 3
(TO10 to TO13) of timer output register 0 (TO0) and bits 0 to 3 (TOE10 to TOE13) of
timer output enable register 0 (TOE0) to “0”, which is the same as their default status
setting.
p.162
PM0 to PM9,
PM11 to PM16:
Port mode
registers
Be sure to set bits 1 to 4 of PM12, bits 2 to 7 of PM13, bits 6 and 7 of PM14, and bits
4 to 7 of PM16 to ‘‘1’’. And be sure to set bit 0 of PM13 to ‘‘0’’.
p.164
Set the channel used for A/D conversion to the input mode by using port mode
registers 2 and 15 (PM2, PM15).
p.171
Do not set the pin set by ADPC as digital I/O by analog input channel specification
register (ADS).
p.171
ADPC: A/D port
configuration
register
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the
order of P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port
configuration register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 as analog inputs, start designing from P157/ANI15.
p.171
Chapter
4
Soft
Port
functions
1-bit
manipulation
instruction for
port register n
(Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input
and output functions, the output latch value of an input port that is not subject to
manipulation may be written in addition to the targeted bit.
Therefore, it is
recommended to rewrite the output latch when switching a port from input mode to
output mode.
p.179
PER1:
Peripheral
enable register 1
When setting the external bus interface, be sure to set EXBEN to 1 first. If EXBEN =
0, writing to a control register of the external bus interface is ignored, and, even if the
register is read, only the default value is read (except for port mode registers 0, 1, 5,
6, 7, 8, 9 (PM0, PM1, PM5, PM6, PM7, PM8, PM9) and port registers 0, 1, 5, 6, 7, 8,
9 (P0, P1, P5, P6, P7, P8, P9)).
p.185
Chapter
5
Soft
External
bus
interface
Number of
instruction
execution clocks
and instruction
wait clocks for
fetch access
The flash memory and external memory are located in consecutive spaces, but start
fetching in the external memory space by using a branch instruction (CALL, BR) in
the flash memory or RAM memory.
p.189