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参数资料
| 型号： | UT61L256C |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 异步静态RAM高速 |
| 文件页数： | 12/14页 |
| 文件大小： | 114K |
| 代理商： | UT61L256C |
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
7
Notes :
1. WE , CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to
be placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a
high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
DATA RETENTION CHARACTERISTICS (T
A = -20J
to 80J )
PARAMETER
SYMBOL TEST CONDITION
MIN. MAX. UNIT
Vcc for Data Retention
VDR
CE
VCC-0.2V or CE2
≤ 0.2V
2.0
3.6
V
Data Retention Current
IDR
Vcc=2V
CE
VCC-0.2V or CE2
≤ 0.2V
-
3
mA
Chip Disable to Data
Retention Time
tCDR
See Data Retention Waveforms
0
-
ms
Recovery Time
tR
5
-
ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE controlled)
VDR
2V
CE
VCC-0.2V
Vcc(min.)
VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR
2V
VCC(min.)
VCC
tR
tCDR
CE2
0.2V
VIL
CE2
VCC(min.)
VIL
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