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参数资料
| 型号： | UT61L6416(E) |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 异步静态RAM高速 |
| 文件页数： | 9/14页 |
| 文件大小： | 114K |
| 代理商： | UT61L6416(E) |
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
CAPACITANCE (T
A=25J , f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
CIN
-
8
pF
Input/Output Capacitance
CI/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL=30pF, IOH/IOL=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS (V
CC = 3.0V
3.6V , TA = -20J
to 80J )
(1) READ CYCLE
UT61L1024-12
UT61L1024-15
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
12
-
15
-
ns
Address Access Time
tAA
-
12
-
15
ns
Chip Enable Access Time
tACE1, tACE1
-
12
-
15
ns
Output Enable Access Time
tOE
-
6
-
7
ns
Chip Enable to Output in Low Z
tCLZ1*, tCLZ2*
3
-
4
-
ns
Output Enable to Output in Low Z
tOLZ*
0
-
0
-
ns
Chip Disable to Output in High Z
tCHZ1*, tCHZ2*
-
6
-
7
ns
Output Disable to Output in High Z
tOHZ*
-
6
-
7
ns
Output Hold from Address Change
tOH
3
-
3
-
ns
(2) WRITE CYCLE
UT61L1024-12
UT61L1024-15
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
12
-
15
-
ns
Address Valid to End of Write
tAW
10
-
12
-
ns
Chip Enable to End of Write
tCW1, tCW2
10
-
12
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Write Pulse Width
tWP
9
-
10
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Data to Write Time Overlap
tDW
7
-
8
-
ns
Data Hold from End of Write Time
tDH
0
-
0
-
ns
Output Active from End of Write
tOW*
3
-
4
-
ns
Write to Output in High Z
tWHZ*
-
7
-
8
ns
*These parameters are guaranteed by device characterization, but not production tested.
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