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参数资料
| 型号： | UT62256C(E) |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 异步静态RAM高速 |
| 文件页数： | 10/12页 |
| 文件大小： | 94K |
| 代理商： | UT62256C(E) |
UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
7
Notes :
1. WE , CE must be high during all address transitions.
2.A write occurs during the overlap of a low CE , low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = -20J ~80J )
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
VDR
CE
VCC-0.2V
2.0
-
5.5
V
Data Retention Current
IDR
Vcc=3V
- L
-
1
50
A
CE
VCC-0.2V
- LL
-
0.5
20
A
Chip Disable to Data
tCDR
See Data Retention
0
-
ns
Retention Time
Waveforms (below)
Recovery Time
tR
tRC*
-
ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform ( CE controlled)
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| UT62256CLS-35L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32K X 8 BIT LOW POWER CMOS SRAM |
| UT62256CLS-35LL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32K X 8 BIT LOW POWER CMOS SRAM |
| UT62256CLS-70L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32K X 8 BIT LOW POWER CMOS SRAM |
| UT62256CLS-70LL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32K X 8 BIT LOW POWER CMOS SRAM |
| UT62256CPC-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32K X 8 BIT LOW POWER CMOS SRAM |
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