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参数资料
| 型号： | V24C8T100BL3 |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE |
| 文件页数： | 3/13页 |
| 文件大小： | 468K |
| 代理商： | V24C8T100BL3 |
2001 Feb 02
11
NXP Semiconductors
Product specification
Low-cost stereo filter DAC
UDA1330ATS
SYSTEM CLOCK FREQUENCY
The system clock frequency is a 2-bit value to select the
external clock frequency.
Table 8
System clock settings
DATA FORMAT
The data format is a 3-bit value to select the used data
format.
Table 9
Data input format settings
DE-EMPHASIS
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 10 De-emphasis settings
VOLUME CONTROL
The volume control is a 6-bit value to program the volume
attenuation from 0 to
60 dB and ∞ dB in steps of 1 dB.
Table 11 Volume settings
MUTE
Mute is a 1-bit value to enable the digital mute.
Table 12 Mute setting
SC1
SC0
FUNCTION
0
512fs
0
1
384fs
1
0
256fs
1
not used
IF2
IF1
IF0
FORMAT
000
I2S-bus
0
1
LSB-justified 16 bits
0
1
0
LSB-justified 18 bits
0
1
LSB-justified 20 bits
1
0
MSB-justified
1
0
1
not used
1
0
not used
1
not used
DE1
DE0
FUNCTION
0
no de-emphasis
0
1
de-emphasis, 32 kHz
1
0
de-emphasis, 44.1 kHz
1
de-emphasis, 48 kHz
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
000000
0
000001
0
000010
1
000011
2
::::::
:
110011
51
110100
110101
52
110110
110111
54
111000
111001
57
111010
111011
111100
60
111101
111110
∞
111111
MT
FUNCTION
0
no muting
1muting
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