- 您现在的位置：买卖IC网 > PDF目录202171 > V54C316162VAT10 (MOSEL-VITELIC) 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50 PDF资料下载
参数资料
| 型号： | V54C316162VAT10 |
| 厂商： | MOSEL-VITELIC |
| 元件分类： | DRAM |
| 英文描述： | 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-50 |
| 文件页数： | 6/61页 |
| 文件大小： | 916K |
| 代理商： | V54C316162VAT10 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页
14
V54C316162VA Rev. 1.0 January 1998
MOSEL VITELIC
V54C316162VA
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write with Auto-Precharge
8. Burst Termination
8.1 Termination of a full Page Burst Write Operation
8.2 Termination of a Full Page Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 1
12. 2 Clock Suspension During Burst Read CAS Latency = 2
12. 3 Clock Suspension During Burst Read CAS Latency = 3
12. 4 Clock Suspension During Burst Write CAS Latency = 1
12. 5 Clock Suspension During Burst Write CAS Latency = 2
12. 6 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Auto Refresh (CBR)
15. Self Refresh (Entry and Exit)
相关PDF资料 |
PDF描述 |
|---|---|
| V54C3256164VAT6 | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| V54C3256404VDS8IPC | 64M X 4 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| V54C3256404VDUG7 | 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| V54C3256404VDLJ6 | 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| V54C3256404VDUI6 | 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V54C316162VC | 制造商:MOSEL 制造商全称:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-5 | 制造商:MOSEL 制造商全称:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-55 | 制造商:MOSEL 制造商全称:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-6 | 制造商:MOSEL 制造商全称:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-7 | 制造商:MOSEL 制造商全称:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
发布紧急采购，3分钟左右您将得到回复。