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参数资料
| 型号： | V59C1512404QBLF3I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| 封装： | ROHS COMPLIANT, MO-207, FBGA-60 |
| 文件页数： | 1/76页 |
| 文件大小： | 1183K |
| 代理商： | V59C1512404QBLF3I |
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1
V59C1512(404/804/164)QB
HIGH PERFORMANCE 512 Mbit DDR2 SDRAM
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 8Mbit X 16 (164)
PRELIMINARY
V59C1512(404/804/164)QB Rev.1.3 February 2008
5
37
3
25A
25
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Clock Cycle Time (tCK3)
5ns
Clock Cycle Time (tCK4)
5ns
3.75ns
Clock Cycle Time (tCK5)
5ns
3.75ns
3ns
2.5ns
Clock Cycle Time (tCK6)
5ns
3.75ns
3ns
2.5ns
System Frequency (fCK max)
200 MHz
266 MHz
333 MHz
400 MHz
Features
■ High speed data transfer rates with system frequency
up to 400MHz
■ Posted CAS
■ Programmable CAS Latency: 3, 4, 5 and 6
■ Programmable Additive Latency:0, 1, 2, 3, 4 and 5
■ Write Latency=Read Latency-1
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 7.8 us (8192 cycles/64 ms)
■ OCD (Off-Chip Driver Impendance Adjustment)
■ ODT (On-Die Termination)
■ Weak Strength Data-Output Driver Option
■ Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ Differential clock inputs CK and CK
■ JEDEC Power Supply 1.8V ± 0.1V
■ VDDQ=1.8V ± 0.1V
■ Available in 60-ball FBGA for x4 and x8 component or
84 ball FBGA for x16 component
■ PASR Partial Array Self Refresh
■ All inputs & outputs are compatible with SSTL_18 in-
terface
■ tRAS lockout supported
■ Read Data Strobe supported (x8 only)
■ Internal four bank operations with single pulsed RAS
Description
The V59C1512(404/804/164)QB is a four bank DDR
DRAM organized as 4 banks x 32Mbit x 4 (404), 4 banks x
16Mbit x 8 (804), or 4 banks x 8Mbit x 16 (164). The
V59C1512(404/804/164)QB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Available Speed Grade:
-5 (DDR2-400) @ CL 3-3-3
-37 (DDR2-533) @ CL 4-4-4
-3 (DDR2-667) @ CL 5-5-5
-25A (DDR2-800) @ CL 6-6-6
-25 (DDR2-800) @ CL 5-5-5
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
60 ball FBGA
84 ball FBGA
-5
-37
-3
-25A
-25
Std.
L
0°C to 85°C
Blank
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