- 您现在的位置：买卖IC网 > PDF目录276836 > V62/07616-03XE (TEXAS INSTRUMENTS INC) 6.5 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO16 PDF资料下载
参数资料
| 型号： | V62/07616-03XE |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 6.5 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | GREEN, PLASTIC, HTSSOP-16 |
| 文件页数： | 4/35页 |
| 文件大小： | 1132K |
| 代理商： | V62/07616-03XE |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
T
delay +
1000
s (kHz)
ms
(6)
Bias Voltage (VBIAS)
Bootstrap Voltage (BOOT)
Error Amplifier
Voltage Reference
PWM Control and Feed Forward
SLVS684A – JANUARY 2007 – REVISED JULY 2009 ....................................................................................................................................................... www.ti.com
Once the PWRGD pin presents a high impedance (i.e., power is good), a VSENSE pin out-of-bounds condition
forces PWRGD low (i.e., power is bad) after a time delay. This time delay is a function of the switching frequency
and is calculated using equation 6:
The VBIAS regulator provides a stable supply for the internal analog circuits and the low-side gate driver. Up to 1
mA of current can be drawn for use in an external application circuit. The VBIAS pin must have a bypass
capacitor value of 1
F. X7R- or X5R-grade dielectric ceramic capacitors are recommended because of their
stable characteristics over temperature.
The BOOT capacitor obtains its charge cycle by cycle from the VBIAS capacitor. A capacitor from the BOOT pin
to the PH pins is required for operation. The bootstrap connection for the high-side driver must have a bypass
capacitor of 0.1
F.
The VSENSE pin is the error amplifier inverting input. The error amplifier is a true voltage amplifier, with 1.5 mA
of drive capability with a minimum of 60 dB of open-loop voltage gain and a unity-gain bandwidth of 2 MHz.
The
voltage-reference
system
produces
a
precision
reference
signal
by
scaling
the
output
of
a
temperature-stable bandgap circuit. During production testing, the bandgap and scaling circuits are trimmed to
produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset errors in the scaling and error-amplifier circuits.
Signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, PWM latch, and
the adaptive dead-time control logic. During steady-state operation below the current-limit threshold, the PWM
comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is reset, the low-side driver and integrated pulldown MOSFET remain on for a minimum
duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to the valley
voltage. When the ramp begins to charge back up, the low-side driver turns off and the high-side FET turns on.
The peak PWM ramp voltage varies inversely with input voltage to maintain a constant modulator and
power-stage gain of 8 V.
As the PWM ramp voltage exceeds the error-amplifier output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
During transient conditions, the error-amplifier output can be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the internal low-side FET and
driver on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set point,
setting VSENSE to approximately the same voltage as the internal voltage reference. If the error-amplifier output
is low, the PWM latch is reset continually and the high-side FET does not turn on. The internal low-side FET and
low-side driver remain on until the VSENSE voltage decreases to a range that allows the PWM comparator to
change states. The TPS5435x is capable of sinking current through the external low-side FET until the output
voltage reaches the regulation set point.
The minimum on time is designed to be 180 ns. During the internal slow-start interval, the internal reference
ramps from 0 V to 0.891 V. During the initial slow-start interval, the internal reference voltage is very small,
resulting in skipped pulses because the minimum on time causes the actual output voltage to be slightly greater
than the preset output voltage, until the internal reference ramps up.
12
Copyright 2007–2009, Texas Instruments Incorporated
相关PDF资料 |
PDF描述 |
|---|---|
| V48B28H250BF3 | 1-OUTPUT 250 W DC-DC REG PWR SUPPLY MODULE |
| V48B36H250BF | 1-OUTPUT 250 W DC-DC REG PWR SUPPLY MODULE |
| VRAH-03E2500 | 1-OUTPUT 7.5 W DC-DC REG PWR SUPPLY MODULE |
| V300C15C150AN | 1-OUTPUT 150 W DC-DC REG PWR SUPPLY MODULE |
| V300C28C150AN | 1-OUTPUT 150 W DC-DC REG PWR SUPPLY MODULE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V62-08631-01XE | 制造商:TI 制造商全称:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLER |
| V62-09601-01XE | 制造商:TI 制造商全称:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLER |
| V62-09620-01XA | 制造商:TI 制造商全称:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLER |
| V620H011M | 制造商:OMRON Industrial Automation 功能描述: 制造商:Omron Corporation 功能描述: |
| V620H015M | 制造商:OMRON Industrial Automation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。