参数资料
型号: VC-710-DFF-GFL-139.264
厂商: VECTRON INTERNATIONAL
元件分类: XO, clock
英文描述: VCXO, CLOCK, 139.264 MHz, LVPECL OUTPUT
封装: ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6
文件页数: 2/6页
文件大小: 0K
代理商: VC-710-DFF-GFL-139.264
VC-710 Voltage Controlled Crystal Oscillator
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Tel: 1-88-VECTRON-1
Website: www.vectron.com
Page 2 of 6
Rev: December 13, 2006
Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Frequency
fO
80
155.52
200
MHz
Supply Voltage
(+3.3 V)
VDD
3.135
3.3
3.465
V
Supply Current
IDD
50
90
mA
Output Logic Levels
Output Logic High
+25 C
Output Logic Low
+25 C
VOH
VOL
Vcc -1.025
Vcc -1.810
Vcc -0.950
Vcc -1.700
Vcc -0.880
Vcc -1.620
V
Transition Times
Rise Time
Fall Time
tR
tF
0.5
1
ns
Symmetry or Duty Cycle
SYM
45
50
55
%
Operating temperature (ordering option)
0/70 or –40/85
°C
Jitter (12 kHz – 20 MHz BW), 155.52 MHz
0.3
ps (rms)
Jitter (50 kHz – 80 MHz BW), 155.52 MHz
0.5
ps (rms)
Phase Noise, f0 = 155.52 MHz
10 Hz offset
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
-64
-95
-123
-143
-146
dBc/Hz
Test Conditions for APR (+3.3V)
VC
0.3
3.0
V
Absolute Pull Range (APR)
APR
+ 50
ppm
Gain Transfer
Positive, 65
ppm/V
Control Voltage Bandwidth (-3dB)
BW
20
100
kHz
Enable/Disable
1
Output Enabled, F option
Output Disabled, F option
Output Enabled, B option
Output Disabled, B option
VDD*0.7
VDD*0.3
VDD*0.2
V
Package Size
5.08 x 7.5 x 1.8
mm
1. Output is enabled if the E/D, pin 2, is left open on F option. E/D must be terminated on B option.
VOL
50%
VOH
80%
20%
tR
tF
tA
tB
SYM = 100 x tA / tB
Figure 2. PECL Waveform
1
2
3
6
5
4
50
Test Circuit Notes:
1) To Permit 50 Measurement of O utputs, all DC Inputs are Biased Down 1.3V.
2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise.
3) 50 Terminations are W ithin Test Equipment.
(-1.3V to +2V)
(-1.3V)
(+2V)
CO utput
Output
>1.4V or O pen
Figure 1. Test Circuit ( 3.3 V)
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