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参数资料
| 型号： | VCC6-VAG-166M666700 |
| 厂商： | VECTRON INTERNATIONAL |
| 元件分类： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 166.6667 MHz, LVDS OUTPUT |
| 封装： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6 |
| 文件页数： | 5/7页 |
| 文件大小： | 186K |
| 代理商： | VCC6-VAG-166M666700 |
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
LVPECL Application Diagrams
The VCC6 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes on
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme as
shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
Figure 7. Standard PECL Output Configuration Figure 8. Single Resistor Termination Scheme
Figure 9. Pull-Up Pull Down Termination
Resistor values are typically 140 ohms for
3.3V operation.
Resistor values are typically 84 ohms for 2.5V
operation.
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62
ohms and the resistor to supply is 240 ohms
Environmental and IR Compliance
Table 4. Environmental Compliance
Parameter
Condition
Mechanical Shock
MIL-STD-883 Method 2002
Mechanical Vibration
MIL-STD-883 Method 2007
Temperature Cycle
MIL-STD-883 Method 1010
Solderability
MIL-STD-883 Method 2003
Fine and Gross Leak
MIL-STD-883 Method 1014
Resistance to Solvents
MIL-STD-883 Method 2015
Moisture Sensitivity Level
MSL1
Contact Pads
Gold over Nickel
VCC
OUT+
OUT-
100
LVDS
Driver
LVDS
Receiver
100
LVDS
Driver
Receiver
Figure 10 Standard LVDS
Output Configuration
Figure 11. LVDS to LVDS Connection, Internal 100ohm
Figure 12. LVDS to LVDS Connection
External 100ohm and AC blocking caps
Some LVDS structures have an internal 100 ohm resistor on the
input and do not need additional components.
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
LVDS Application Diagrams
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
140Ω
Page5
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