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参数资料
| 型号： | VDRIVE2 |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | MOD USB FLASH DRIVE INTERFACE |
| 产品培训模块： | USB Introduction |
| 产品目录绘图： | VDRIVE2 |
| 标准包装： | 5 |
| 系列： | Vinculum |
| 附件类型： | USB 接口模块 |
| 适用于相关产品： | 闪存驱动器 |
| 产品目录页面： | 634 (CN2011-ZH PDF) |
| 其它名称： | 768-1003 |
2.3 SPI Interface Signal Descriptions and Timing Diagrams
Ta?le 3 - Data and Control ??us ?ignal Mode ?ptions - ??I Inter?ace
Page
Pin No.
?
4
2
6
Name
?CLK
?DI
?D?
C?
Type
Input
Input
?utput
Input
Description
??I Cloc? input?? 12MHz ma?imum.
??I ?erial Data Input
??I ?erial Data ?utput
??I Chip ?elect Input
Figure 2 - ??I ?lave Data ?ead Cycle
R/W ADD D7
D6
D5
D4
D3
D2
D1
D0
SPICLK
SPI CS
SPI Data In
1
1
0
SPI Data Out
From ?tart - ??I C? must ?e held high ?or the entire read cycle?? and must ?e ta?en low ?or at least one cloc? period
aft?r th? r?ad i? co??p??t?d. Th? fir?t bit on S??I Data In i? th? R/W bit - inp?tting a ‘1’ h?r? a??o?? data to b? r?ad fro??
the chip. The ne?t ?it is the address ?it?? ?DD?? which is used to indicate whether the data register (?0?) or the status
register (?1?) is read ?rom. During the ??I read cycle a ?yte o? data will start ?eing output on ??I Data ?ut on the ne?t
c?ock cyc?? aft?r th? addr??? bit?? MSB fir?t. ?ft?r th? data ha? b??n c?ock?d o?t of th? chip?? th? ?tat?? of S??I Data
?ut should ?e chec?ed to see i? the data read is new data. ? ?0? level here on ??I Data ?ut means that the data read
is new data. ? ?1? indicates that the data read is old data?? and the read cycle should ?e repeated to get new data.
?emem?er that C? must ?e held low ?or at least one cloc? period ?e?ore ?eing ta?en high again to continue with the
ne?t read or write cycle.
Figure 3 - ??I ?lave Data Write Cycle
R/W ADD D7
D6
D5
D4
D3
D2
D1
D0
SPICLK
SPI CS
SPI Data In
1
0
0
SPI Data Out
From ?tart - ??I C? must ?e held high ?or the entire write cycle?? and must ?e ta?en low ?or at least one cloc? period
aft?r th? ?rit? i? co??p??t?d. Th? fir?t bit on S??I Data In i? th? R/W bit - inp?tting a ‘0’ h?r? a??o?? data to b? ?ritt?n
to the chip. The ne?t ?it is the address ?it?? ?DD?? which is used to indicate whether the data register (?0?) or the status
register (?1?) is written to. During the ??I write cycle a ?yte o? data can ?e input to ??I Data In on the ne?t cloc? cycle
aft?r th? addr??? bit?? MSB fir?t. ?ft?r th? data ha? b??n c?ock?d in to th? chip?? th? ?tat?? of S??I Data O?t ?ho??d b?
VDrive2 Vinculum VNC1L Module
Datasheet Version 0.99
? Future Technology Devices International Ltd. 2007
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