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参数资料
| 型号： | VIC64-UC |
| 英文描述： | VME/VMS/VXI/VSB Bus Interface/Controller |
| 中文描述： | VME总线/威迈斯/ VXI总线/兽医管理局总线接口/控制器 |
| 文件页数： | 1/13页 |
| 文件大小： | 833K |
| 代理商： | VIC64-UC |
VMEbus Interface Controller
with D64 Functionality
VIC64
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-09002 Rev. **
Revised July 22, 1997
Features
An enhanced VIC068A
— 64-bit MBLT operation
— Higher transfer rate
Complete VMEbus interface controller and arbiter
— 58 internal registers for configuration control and
VMEbus and local operations status
— Drives arbitration, interrupt, address modifier, utility,
strobe, address line A[7:1], and data line D[7:0] di-
rectly and provides control signals to drive remain-
ing address and data lines
— Direct connection to 68K family and mappable to
non-68K processors
Complete master/slave capability
— Supports read, write, write posting, and block trans-
fers
— Accommodates VMEbus timing requirements with
internal digital delay line with half-clock granularity
— Programmable metastability delay
— Programmable data acquisition delays
— Provides programmable timeout timers for local bus
and VMEbus transactions
Interleaved block transfers
— D64 block transfer capability in conformance with
VME64 proposal
— Can act as DMA master on local bus
— Programmable burst counter, transfer length, and in-
terleave period
— Allows master and slave transfer to occur during in-
terleave period
— Also supports local module-based DMA
Arbitration support
— Supports single-level, priority, and round-robin arbi-
tration
— Support fair request option as requester
Interrupt support
— Complete support for the VMEbus interrupts; inter-
rupters and interrupt handler
— Seven local interrupt lines
— 8-level interrupt priority encoded
— Total of 29 interrupts mapped through the VIC64
Miscellaneous features
— Refresh option for local DRAM
— Four broadcast location monitors
— Four module-specific location monitors
— Eight interprocessor communication registers
See the VMEbus Interface Handbook for more informa-
tion
Functional Description
Cypress’s VIC64 VMEbus Interface Controller with D64 func-
tionality is a single chip designed to minimize the cost and
board area requirements and to maximize the performance of
a VMEbus master/slave module. Data transfers of 70
Mbyte/sec are possible between boards using VIC64.
In addition to D8, D16, and D32 operations, the VIC64 per-
forms D64 data transfer. On-chip output buffers are used to
provide direct connection to address and data lines.
The VIC64 is based on the industry-standard VIC068A. For
most applications, the VIC64 is fully software and plug com-
patible with the VIC068A. (As VIC64 uses register bits that
are unassigned in VIC068A, user code may require simple
rework to insure compatibility.)
The local bus interface of the VIC64 emulates Motorola’s fam-
ily of 32-bit 68K processor interfaces. Other processors can
easily be adapted to interface to the VIC64 using appropriate
logic.
Resetting the VIC64
The VIC64 can be reset by any of three distinct reset condi-
tions:
Internal Reset. This reset is the most common means of
resetting the VIC64. It resets selected register values and
logic within the device.
System Reset. This reset provides a means of resetting the
VIC64 through the VMEbus backplane. The VIC64 may also
initiate a system reset by writing a configuration register.
Global Reset. This provides the most complete reset of the
VIC64. It resets all of the VIC64’s configuration registers.
All three reset options are implemented in a different manner
and have different effect on the VIC64 configuration registers.
VIC64 VMEbus System Controller
The VIC64 is capable of operating as the VMEbus system con-
troller. It provides VMEbus arbitration functions, including:
Priority, round-robin, and single-level arbitration schemes
Driving IACK daisy-chain
Driving BGiOUT daisy-chain (all four levels)
Driving SYSCLK output
VMEbus arbitration timeout timer
The system controller functions are enabled by the SCON pin
of the VIC64. This pin is sampled during Reset and if LOW,
VIC64 performs as system controller. After Reset the pin be-
comes an output signifying a D64 transfer.
VIC64 VMEbus Master Cycles
The VIC64 is capable of becoming the VMEbus master in re-
sponse to a request from local resources. In this situation, the
local resource requests a VMEbus transfer. The VIC64 makes
a request for the VMEbus. When the VMEbus is granted to the
VIC64, it then performs the transfer and acknowledges the lo-
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