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参数资料
| 型号： | VS8061FI |
| 厂商： | VITESSE SEMICONDUCTOR CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, CQFP52 |
| 封装： | HEAT SINK, CERAMIC, LDCC-52 |
| 文件页数： | 1/20页 |
| 文件大小： | 409K |
| 代理商： | VS8061FI |
VITESSE SEMICONDUCTOR CORPORATION
Page 1
6/22/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Datsheet
VSC8061/VSC8062
2.5 Gb/s 16-Bit Multiplexer/
Demultiplexer Chipset
G52069-0, Rev. 4.1
Features
Functional Description
The VS8061 and VS8062 are high speed interface devices capable of data rates up to 2.5 Gb/s. These
devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve high
speed and low power dissipation. For ease of system design using these products, both devices use industry
standard, -5.2V and -2V, power supplies, and have ECL compatible I/O for parallel data interfaces. Typical
applications include telecommunication transmission and instrumentation.
VS8061 Multiplexer
The VS8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates a
divide-by-16 clock from the high speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended ECL
compatible inputs (D0..D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial output
(DO/DON). The internal timing of the VS8061 is referenced to the negative going edge of the high speed clock
true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The setup and
hold time of the parallel inputs (D0..D15) are specified with respect to the falling edge of CLK16, so that
CLK16/CLK16N can be used to clock the data source of D0..D15. The on-chip phase detector monitors the
phase relationship between the internally generated divide by 16 clock and an externally supplied low speed ref-
erence clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or down
output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase Locked
Loop (PLL) to implement a clock multiplication function.
In applications where a 2.5 GHz system clock is provided, and the phase detector function is not required, it
is recommended to connect one side of the DCLK/DCLKN input to V
TT through a 50 ohm resistor. The U and D
output can be left open and unused.
VS8062 Demultiplexer
The VS8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock
from the high speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s
and deserializes it into 16 parallel single-ended ECL compatible outputs (D0..D15) at data rates up to 156 Mb/s.
The internal timing of the VS8062 is referenced to the negative going edge of the high speed clock true input
(CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the
parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so that CLK16/
CLK16N can be used to clock the destination of D0..D15.
Serial Data Rate up to 2.5 Gb/s
16-bit Wide ECL 100K Compatible Parallel
Data Interface
Differential High Speed Data Outputs
Differential or Single-ended High Speed Data
and Clock Inputs
On-chip Phase Detector (VS8061 Multiplexer)
Power Dissipation: VS8061: 2.0W(max),
VS8062: 1.7W(max)
Standard ECL Power Supplies: V
EE = -5.2
volts, V
TT = -2.0 volts
Commercial (0
o to 70o C) or Industrial (-40o C
to 85
o C) Temperature Range
Available in 52-pin Ceramic Leaded Chip Car-
rier Package or 52-pin Plastic Quad Flat Pack
相关PDF资料 |
PDF描述 |
|---|---|
| VS8061FC | SPECIALTY TELECOM CIRCUIT, CQFP52 |
| VS8062FI | SPECIALTY TELECOM CIRCUIT, CQFP52 |
| VS8062FC | SPECIALTY TELECOM CIRCUIT, CQFP52 |
| VS9ASH-150.000 | VCXO, CLOCK, 150 MHz, PECL OUTPUT |
| VS9ARG-150.000 | VCXO, CLOCK, 150 MHz, PECL OUTPUT |
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