参数资料
型号: W110
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器杂项-数据表参考
文件页数: 15/20页
文件大小: 383K
代理商: W110
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W110 Dual-Speed Ethernet Controller
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15
Oki Semiconductor
Address Recognition
The W110 does not perform address recognition in the body of the MAC. Address recognition is per-
formed downstream on the receive byte stream. This arrangement improves the design of multiple-MAC
implementations. In multiple-MAC implementations, the receive byte streams from several MACs can be
directed to a central address recognition logic block. This common arrangement reduces gate count,
speeds processing and improves management access and control. OKI does support a separate block to
perform address recognition. Please contact OKI ASIC Application Engineering for more information.
Host Interface Options
The W110 connects to a host system of a customer-specified type. Many different types of host interface
may be used. Examples include sophisticated bus-mastering types such as PCI, shared memory, ring-
buffer, DMA and FIFO-based designs. In a switch system, the host generally is an embedded CPU or a
backplane switching fabric. In a general network interface, the host might be a general purpose computer
communicating over the computer bus. The W110 communicates to the host system using generalized
receive and transmit byte streams. Oki can provide an additional module for interfacing to 16-, 32-, or 64-
bit host interfaces with DMA and FIFO.
Figure 9. Example of W110 Interface to Host System
Testing
OKI Semiconductor provides appropriate test vectors to verify the timing and functionality of each design
implementation. OKI also creates appropriate test bench modules during development. Contact the Oki
ASIC Application Engineering Department for more information.
Host
System
Address
Recognition Logic
Receive
Byte Stream Logic
Transmit
Byte Stream Logic
Host Processor
Interface
Statistics Vector
Interface
W110
Dual-Speed
MAC
Transmit Byte Stream
Receive Byte Stream
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