W158
Document #: 38-07164 Rev. *A
Page 9 of 13
Note:
37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
t
P
Period
t
H
High Time
Duration of clock cycle above 2.4V
t
L
Low Time
Duration of clock cycle below 0.4V
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
t
SK
Output Skew
Measured on rising edge at 1.5V
t
O
3V66 to PCI Clock
Skew
1.5V. 3V66 leads PCI output.
t
q
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at
1.5V. CPU leads PCI output.
f
ST
Frequency Stabilization
from Power-up (cold
start)
Z
o
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
Test Condition/Comments
Min.
30
12
12
1
1
45
Typ.
Max.
Unit
ns
ns
ns
V/ns
V/ns
%
ps
Measured on rising edge at 1.5V
[37]
4
4
55
500
500
3
ps
ns
Covers all 3V66/PCI outputs. Measured on rising edge at
1.5
1.5
4
ns
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3
ms
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization from
Power-up (cold start)
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
14.318
Max.
Unit
MHz
V/ns
V/ns
%
ms
0.5
0.5
45
2
2
55
3
Z
o
AC Output Impedance
25
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f
D
Deviation from 48 MHz
m/n
PLL Ratio
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization
from Power-up (cold start)
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008
–
48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
48.008
+167
57/17
Max.
Unit
MHz
ppm
0.5
0.5
45
2
2
V/ns
V/ns
%
ms
55
3
Z
o
AC Output Impedance
25